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| 型號： | ATMEGA324P-B15MZ |
| 廠商： | Atmel |
| 文件頁數(shù)： | 25/70頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 32KB FLASH 44VQFN |
| 標準包裝： | 4,000 |
| 系列： | AVR® ATmega |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 32KB（16K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 1K x 8 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 44-VFQFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | ATMEGA324P-B15MZ-ND |
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2011 Microchip Technology Inc.
DS41391D-page 243
PIC16(L)F1826/27
When one device is transmitting a logical one, or letting
the line float, and a second device is transmitting a log-
ical zero, or holding the line low, the first device can
detect that the line is not a logical one. This detection,
when used on the SCLx line, is called clock stretching.
Clock stretching gives slave devices a mechanism to
control the flow of data. When this detection is used on
the SDAx line, it is called arbitration. Arbitration
ensures that there is only one master device communi-
cating at any single time.
25.3.1
CLOCK STRETCHING
When a slave device has not completed processing
data, it can delay the transfer of more data through the
process of Clock Stretching. An addressed slave
device may hold the SCLx clock line low after receiving
or sending a bit, indicating that it is not yet ready to con-
tinue. The master that is communicating with the slave
will attempt to raise the SCLx line in order to transfer
the next bit, but will detect that the clock line has not yet
been released. Because the SCLx connection is
open-drain, the slave has the ability to hold that line low
until it is ready to continue communicating.
Clock stretching allows receivers that cannot keep up
with a transmitter to control the flow of incoming data.
25.3.2
ARBITRATION
Each master device must monitor the bus for Start and
Stop bits. If the device detects that the bus is busy, it
cannot begin a new message until the bus returns to an
Idle state.
However, two master devices may try to initiate a trans-
mission on or about the same time. When this occurs,
the process of arbitration begins. Each transmitter
checks the level of the SDAx data line and compares it
to the level that it expects to find. The first transmitter to
observe that the two levels don't match, loses arbitra-
tion, and must stop transmitting on the SDAx line.
For example, if one transmitter holds the SDAx line to
a logical one (lets it float) and a second transmitter
holds it to a logical zero (pulls it low), the result is that
the SDAx line will be low. The first transmitter then
observes that the level of the line is different than
expected and concludes that another transmitter is
communicating.
The first transmitter to notice this difference is the one
that loses arbitration and must stop driving the SDAx
line. If this transmitter is also a master device, it also
must stop driving the SCLx line. It then can monitor the
lines for a Stop condition before trying to reissue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDAx line continues with it's
original transmission. It can do so without any compli-
cations, because so far, the transmission appears
exactly as expected with no other transmitter disturbing
the message.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less com-
mon.
If two master devices are sending a message to two dif-
ferent slave devices at the address stage, the master
sending the lower slave address always wins arbitra-
tion. When two master devices send messages to the
same slave address, and addresses can sometimes
refer to multiple slaves, the arbitration process must
continue into the data stage.
Arbitration usually occurs very rarely, but it is a neces-
sary process for proper multi-master support.
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| ATMEGA324PB-AN | 功能描述:IC MCU 8BIT 32KB FLASH 44TQFP 制造商:microchip technology 系列:AVR? ATmega 包裝:托盤 零件狀態(tài):在售 核心處理器:AVR 核心尺寸:8-位 速度:20MHz 連接性:I2C，SPI，UART/USART 外設(shè):欠壓檢測/復(fù)位，POR，PWM，WDT I/O 數(shù):39 程序存儲容量:32KB（16K x 16） 程序存儲器類型:閃存 EEPROM 容量:1K x 8 RAM 容量:2K x 8 電壓 - 電源（Vcc/Vdd）:1.8 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器類型:內(nèi)部 工作溫度:-40°C ~ 105°C（TA） 封裝/外殼:44-TQFP 供應(yīng)商器件封裝:44-TQFP 標準包裝:160 |
| ATMEGA324PB-ANR | 功能描述:IC MCU 8BIT 32KB FLASH 44TQFP 制造商:microchip technology 系列:AVR? ATmega 包裝:剪切帶（CT） 零件狀態(tài):在售 核心處理器:AVR 核心尺寸:8-位 速度:20MHz 連接性:I2C，SPI，UART/USART 外設(shè):欠壓檢測/復(fù)位，POR，PWM，WDT I/O 數(shù):39 程序存儲容量:32KB（16K x 16） 程序存儲器類型:閃存 EEPROM 容量:1K x 8 RAM 容量:2K x 8 電壓 - 電源（Vcc/Vdd）:1.8 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器類型:內(nèi)部 工作溫度:-40°C ~ 105°C（TA） 封裝/外殼:44-TQFP 供應(yīng)商器件封裝:44-TQFP 標準包裝:1 |
| ATMEGA324PB-AU | 功能描述:IC MCU 8BIT 32KB FLASH 44TQFP 制造商:microchip technology 系列:AVR? ATmega 包裝:散裝 零件狀態(tài):在售 核心處理器:AVR 核心尺寸:8-位 速度:20MHz 連接性:I2C，SPI，UART/USART 外設(shè):欠壓檢測/復(fù)位，POR，PWM，WDT I/O 數(shù):39 程序存儲容量:32KB（16K x 16） 程序存儲器類型:閃存 EEPROM 容量:1K x 8 RAM 容量:2K x 8 電壓 - 電源（Vcc/Vdd）:1.8 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器類型:內(nèi)部 工作溫度:-40°C ~ 85°C（TA） 封裝/外殼:44-TQFP 供應(yīng)商器件封裝:44-TQFP 標準包裝:160 |
| ATMEGA324PB-AUR | 功能描述:IC MCU 8BIT 32KB FLASH 44TQFP 制造商:microchip technology 系列:AVR? ATmega 包裝:帶卷（TR） 零件狀態(tài):在售 核心處理器:AVR 核心尺寸:8-位 速度:20MHz 連接性:I2C，SPI，UART/USART 外設(shè):欠壓檢測/復(fù)位，POR，PWM，WDT I/O 數(shù):39 程序存儲容量:32KB（16K x 16） 程序存儲器類型:閃存 EEPROM 容量:1K x 8 RAM 容量:2K x 8 電壓 - 電源（Vcc/Vdd）:1.8 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器類型:內(nèi)部 工作溫度:-40°C ~ 85°C（TA） 封裝/外殼:44-TQFP 供應(yīng)商器件封裝:44-TQFP 標準包裝:2,000 |
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