參數(shù)資料
型號(hào)： ATMEGA324P-B15MZ
廠商： Atmel
文件頁(yè)數(shù)： 35/70頁(yè)
文件大小： 0K
描述： IC MCU 8BIT 32KB FLASH 44VQFN
標(biāo)準(zhǔn)包裝： 4,000
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 16MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 32KB（16K x 16）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 44-VFQFN 裸露焊盤(pán)
包裝： 帶卷 (TR)
其它名稱(chēng)： ATMEGA324P-B15MZ-ND
PIC16(L)F1826/27
DS41391D-page 252
2011 Microchip Technology Inc.
25.5.3
SLAVE TRANSMISSION
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPxSTAT register is set. The received address is
loaded into the SSPxBUF register, and an ACK pulse is
sent by the slave on the ninth bit.
Following the ACK, slave hardware clears the CKP bit
and the SCLx pin is held low (see Section 25.5.6
for more detail). By stretching the
clock, the master will be unable to assert another clock
pulse until the slave is done preparing the transmit
data.
The transmit data must be loaded into the SSPxBUF
register which also loads the SSPxSR register. Then
the SCLx pin should be released by setting the CKP bit
of the SSPxCON1 register. The eight data bits are
shifted out on the falling edge of the SCLx input. This
ensures that the SDAx signal is valid during the SCLx
high time.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCLx input pulse. This ACK
value is copied to the ACKSTAT bit of the SSPxCON2
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. In this case, when the not ACK is
latched by the slave, the slave goes Idle and waits for
another occurrence of the Start bit. If the SDAx line was
low (ACK), the next transmit data must be loaded into
the SSPxBUF register. Again, the SCLx pin must be
released by setting bit CKP.
An MSSPx interrupt is generated for each data transfer
byte. The SSPxIF bit must be cleared by software and
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of
the ninth clock pulse.
25.5.3.1
Slave Mode Bus Collision
A slave receives a Read request and begins shifting
data out on the SDAx line. If a bus collision is detected
and the SBCDE bit of the SSPxCON3 register is set,
the BCLxIF bit of the PIRx register is set. Once a bus
collision is detected, the slave goes Idle and waits to be
addressed again. User software can use the BCLxIF bit
to handle a slave bus collision.
25.5.3.2
7-bit Transmission
A master device can transmit a read request to a
slave, and then clock data out of the slave. The list
below outlines what software for a slave will need to
do
to
accomplish
a
standard
transmission.
Figure 25-17 can be used as a reference to this list.
1.
Master sends a Start condition on SDAx and
SCLx.
2.
S bit of SSPxSTAT is set; SSPxIF is set if inter-
rupt on Start detect is enabled.
3.
Matching address with R/W bit set is received by
the Slave setting SSPxIF bit.
4.
Slave hardware generates an ACK and sets
SSPxIF.
5.
SSPxIF bit is cleared by user.
6.
Software reads the received address from
SSPxBUF, clearing BF.
7.
R/W is set so CKP was automatically cleared
after the ACK.
8.
The slave software loads the transmit data into
SSPxBUF.
9.
CKP bit is set releasing SCLx, allowing the mas-
ter to clock the data out of the slave.
10. SSPxIF is set after the ACK response from the
master is loaded into the ACKSTAT register.
11. SSPxIF bit is cleared.
12. The slave software checks the ACKSTAT bit to
see if the master wants to clock out more data.
13. Steps 9-13 are repeated for each transmitted
byte.
14. If the master sends a not ACK; the clock is not
held, but SSPxIF is still set.
15. The master sends a Restart condition or a Stop.
16. The slave is no longer addressed.
Note 1:
If the master ACKs the clock will be
stretched.
2:
ACKSTAT is the only bit updated on the
rising edge of SCLx (9th) rather than the
falling.
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