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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ATMEGA324P-B15MZ |
| 寤犲晢锛� | Atmel |
| 鏂囦欢闋佹暩(sh霉)锛� | 24/70闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU 8BIT 32KB FLASH 44VQFN |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 4,000 |
| 绯诲垪锛� | AVR® ATmega |
| 鏍稿績铏曠悊鍣細 | AVR |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 16MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 32 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 32KB锛�16K x 16锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶у皬锛� | 1K x 8 |
| RAM 瀹归噺锛� | 2K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 8x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 灏佽/澶栨锛� | 44-VFQFN 瑁搁湶鐒婄洡 |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 鍏跺畠鍚嶇ū锛� | ATMEGA324P-B15MZ-ND |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�鐣�(d膩ng)鍓嶇24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�
PIC16(L)F1826/27
DS41391D-page 242
2011 Microchip Technology Inc.
25.3
I2C
MODE OVERVIEW
The Inter-Integrated Circuit Bus (IC) is a multi-master
serial data communication bus. Devices communicate
in a master/slave environment where the master
devices initiate the communication. A Slave device is
controlled through addressing.
The I2C bus specifies two signal connections:
Serial Clock (SCLx)
Serial Data (SDAx)
Figure 25-11 shows the block diagram of the MSSPx
module when operating in I2C Mode.
Both the SCLx and SDAx connections are bidirectional
open-drain lines, each requiring pull-up resistors for the
supply voltage. Pulling the line to ground is considered
a logical zero and letting the line float is considered a
logical one.
Figure 25-11 shows a typical connection between two
processors configured as master and slave devices.
The I2C bus can operate with one or more master
devices and one or more slave devices.
There are four potential modes of operation for a given
device:
Master Transmit mode
(master is transmitting data to a slave)
Master Receive mode
(master is receiving data from a slave)
Slave Transmit mode
(slave is transmitting data to a master)
Slave Receive mode
(slave is receiving data from the master)
To begin communication, a master device starts out in
Master Transmit mode. The master device sends out a
Start bit followed by the address byte of the slave it
intends to communicate with. This is followed by a sin-
gle Read/Write bit, which determines whether the mas-
ter intends to transmit to or receive data from the slave
device.
If the requested slave exists on the bus, it will respond
with an Acknowledge bit, otherwise known as an ACK.
The master then continues in either Transmit mode or
Receive mode and the slave continues in the comple-
ment, either in Receive mode or Transmit mode,
respectively.
A Start bit is indicated by a high-to-low transition of the
SDAx line while the SCLx line is held high. Address and
data bytes are sent out, Most Significant bit (MSb) first.
The Read/Write bit is sent out as a logical one when the
master intends to read data from the slave, and is sent
out as a logical zero when it intends to write data to the
slave.
FIGURE 25-11:
I2C MASTER/
SLAVE CONNECTION
The Acknowledge bit (ACK) is an active-low signal,
which holds the SDAx line low to indicate to the trans-
mitter that the slave device has received the transmit-
ted data and is ready to receive more.
The transition of a data bit is always performed while
the SCLx line is held low. Transitions that occur while
the SCLx line is held high are used to indicate Start and
Stop bits.
If the master intends to write to the slave, then it repeat-
edly sends out a byte of data, with the slave responding
after each byte with an ACK bit. In this example, the
master device is in Master Transmit mode and the
slave is in Slave Receive mode.
If the master intends to read from the slave, then it
repeatedly receives a byte of data from the slave, and
responds after each byte with an ACK bit. In this exam-
ple, the master device is in Master Receive mode and
the slave is Slave Transmit mode.
On the last byte of data communicated, the master
device may end the transmission by sending a Stop bit.
If the master device is in Receive mode, it sends the
Stop bit in place of the last ACK bit. A Stop bit is indi-
cated by a low-to-high transition of the SDAx line while
the SCLx line is held high.
In some cases, the master may want to maintain con-
trol of the bus and re-initiate another transmission. If
so, the master device may send another Start bit in
place of the Stop bit or last ACK bit when it is in receive
mode.
The I2C bus specifies three message protocols;
Single message where a master writes data to a
slave.
Single message where a master reads data from
a slave.
Combined message where a master initiates a
minimum of two writes, or two reads, or a
combination of writes and reads, to one or more
slaves.
Master
SCLx
SDAx
SCLx
SDAx
Slave
VDD
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鍙冩暩(sh霉)鎻忚堪 |
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| ATMEGA324PB-AN | 鍔熻兘鎻忚堪:IC MCU 8BIT 32KB FLASH 44TQFP 鍒堕€犲晢:microchip technology 绯诲垪:AVR? ATmega 鍖呰:鎵樼洡 闆朵欢鐙€鎱�(t脿i):鍦ㄥ敭 鏍稿績铏曠悊鍣�:AVR 鏍稿績灏哄:8-浣� 閫熷害:20MHz 閫ｆ帴鎬�:I2C锛孲PI锛孶ART/USART 澶栬ō(sh猫):娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛孭WM锛學DT I/O 鏁�(sh霉):39 绋嬪簭瀛樺劜瀹归噺:32KB锛�16K x 16锛� 绋嬪簭瀛樺劜鍣ㄩ鍨�:闁冨瓨 EEPROM 瀹归噺:1K x 8 RAM 瀹归噺:2K x 8 闆诲 - 闆绘簮锛圴cc/Vdd锛�:1.8 V ~ 5.5 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 8x10b 鎸暕鍣ㄩ鍨�:鍏�(n猫i)閮� 宸ヤ綔婧害:-40掳C ~ 105掳C锛圱A锛� 灏佽/澶栨:44-TQFP 渚涙噳(y墨ng)鍟嗗櫒浠跺皝瑁�:44-TQFP 妯�(bi膩o)婧�(zh菙n)鍖呰:160 |
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