參數(shù)資料
型號(hào): ATMEGA324A-MCHR
廠商: Atmel
文件頁數(shù): 72/160頁
文件大小: 0K
描述: IC MCU AVR 32K 20MHZ 44QFN
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
megaAVR Introduction
標(biāo)準(zhǔn)包裝: 6,000
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 32KB(16K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VQFN 裸露焊盤
包裝: 帶卷 (TR)
其它名稱: ATMEGA324A-MCHR SL383
ATMEGA324A-MCHR-ND
ATMEGA324A-MCHRTR
19
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
8.
AVR memories
8.1
Overview
T h is se ction d escr ib es the d if fere nt me mo rie s in the A tm el
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. The AVR architecture has two
main memory spaces, the Data Memory and the Program Memory space. In addition, the
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P features an EEPROM Memory for
data storage. All three memory spaces are linear and regular.
8.2
In-System Reprogrammable Flash Program Memory
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P contains 16/32/64/128Kbytes
On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instruc-
tions are 16 or 32 bits wide, the Flash is organized as 32/64 x 16. For software security, the
Flash Program memory space is divided into two sections, Boot Program section and Applica-
tion Program section.
The F lash memory has an endurance of at least 10,000 write/erase cycles. The
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Program Counter (PC) is 15/16
bits wide, thus addressing the 32/64K program memory locations. The operation of Boot Pro-
gram section and associated Boot Lock bits for software protection are described in detail in
description on Flash data serial downloading using the SPI pins or the JTAG interface.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory instruction description.
Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution Tim-
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