參數(shù)資料
型號(hào)： XR16V2552IL-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 1/46頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 16B DUAL 32QFN
標(biāo)準(zhǔn)包裝： 490
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 16 字節(jié)
規(guī)程： RS232，RS422
電源電壓： 2.25 V ~ 3.6 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤(pán)（5x5）
包裝： 托盤(pán)
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XR16V2552
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
MARCH 2010
REV. 1.0.3
GENERAL DESCRIPTION
The XR16V25521 (V2552) is a high performance dual
universal asynchronous receiver and transmitter
(UART) with 16 byte TX and RX FIFOs. The device
operates from 2.25 to 3.6 volts with 5 Volt tolerant
inputs and is pin-to-pin compatible to Exar’s
ST16C2552 and XR16L2552. The V2552 register set
is compatible to the ST16C2552 and the XR16L2552.
It supports the Exar’s enhanced features of
selectable FIFO trigger level, automatic hardware
(RTS/CTS) and software (Xon/Xoff) flow control, and
a complete modem interface. Onboard registers
provide the user with operational status and data
error flags. An internal loopback capability allows
system diagnostics. Independent programmable
baud rate generators are provided in each channel to
select data rates up to 16 Mbps at 3.3 Volt with 4X
sampling clock. The V2552 is available in 44-pin
PLCC and 32-pin QFN packages.
NOTE: 1 Covered by U.S. Patent #5,649,122
APPLICATIONS
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Controls
FEATURES
2.25 to 3.6 Volt Operation
5 Volt Tolerant Inputs
Pin-to-pin compatible to Exar’s XR16L2552 in the
44-PLCC package
Two independent UART channels
■ Register set identical to 16V2550
■ Data rate of up to 16 Mbps at 3.3 V, and
12.5 Mbps at 2.5 V with 4X sampling rate
■ Fractional Baud Rate Generator
■ Transmit and Receive FIFOs of 16 bytes
■ Selectable TX and RX FIFO Trigger Levels
■ Automatic Hardware (RTS/CTS) Flow Control
■ Automatic Software (Xon/Xoff) Flow Control
■ Wireless Infrared (IrDA 1.0) Encoder/Decoder
■ Automatic sleep mode
■ Full modem interface
Alternate Function Register
Device Identification and Revision
Crystal oscillator (up to 32MHz) or external clock
(up to 64MHz) input
44-PLCC and 32-QFN packages
FIGURE 1. XR16V2552 BLOCK DIAGRAM
XTAL1
XTAL2
Crystal Osc/Buffer
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
8-bit Data
Bus
Interface
UART Channel A
16 Byte TX FIFO
BRG
IR
ENDEC
TX & RX
UART
Regs
2.25 to 3.6 Volt VCC
GND
* 5 Volt Tolerant Inputs
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
UART Channel B
(same as Channel A)
A2:A0
D7:D0
CS#
CHSEL
INTA
INTB
IOW#
IOR#
Reset
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
16 Byte RX FIFO
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