參數(shù)資料
型號: ATMEGA324A-MCHR
廠商: Atmel
文件頁數(shù): 47/160頁
文件大?。?/td> 0K
描述: IC MCU AVR 32K 20MHZ 44QFN
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
megaAVR Introduction
標(biāo)準(zhǔn)包裝: 6,000
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VQFN 裸露焊盤
包裝: 帶卷 (TR)
其它名稱: ATMEGA324A-MCHR SL383
ATMEGA324A-MCHR-ND
ATMEGA324A-MCHRTR
140
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See Section “11.3” on page 55) is executed when the TOV1 Flag, located in TIFR1, is set.
16.12.13 TIMSK3 – Timer/Counter3 Interrupt Mask Register
Bit 7:6 – Reserved
These bits are unused and will always read as zero.
Bit 5 – ICIE3: Timer/Counter3, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (See “Interrupts” on page 61) is executed when the ICF3 Flag, located in TIFR3, is set.
Bit 4:3 – Reserved
These bits are unused and will always read as zero.
Bit 2 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 61) is executed when the OCF3B Flag, located in
TIFR3, is set.
Bit 1 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 61) is executed when the OCF3A Flag, located in
TIFR3, is set.
Bit 0 – TOIE3: Timer/Counter3, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See “Watchdog Timer” on page 55) is executed when the TOV3 Flag, located in TIFR3, is set.
16.12.14 TIFR1 – Timer/Counter1 Interrupt Flag Register
Bit 7:6 – Reserved
These bits are unused and will always read as zero.
Bit
7
65
43
2
1
0
(0x71)
–ICIE3
OCIE3B
OCIE3A
TOIE3
TIMSK3
Read/Write
R
R/W
R
R/W
Initial Value
0
Bit
76543210
–ICF1
OCF1B
OCF1A
TOV1
TIFR1
Read/Write
R
R/W
R
R/W
Initial Value
00000000
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