參數(shù)資料
型號: ATMEGA103-6AI
廠商: Atmel
文件頁數(shù): 115/141頁
文件大?。?/td> 0K
描述: IC MCU 128K 6MHZ A/D IT 64TQFP
產(chǎn)品培訓模塊: megaAVR Introduction
標準包裝: 90
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 6MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
配用: ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
75
ATmega103(L)
0945I–AVR–02/07
Analog Comparator
The analog comparator compares the input values on the positive input PE2 (AC+) and
negative input PE3 (AC-). When the voltage on the positive input PE2 (AC+) is higher
than the voltage on the negative input PE3 (AC-), the Analog Comparator Output (ACO)
is set (one). The output of the comparator can be set to trigger the Timer/Counter1 Input
Capture function. In addition, the comparator can trigger a separate interrupt, exclusive
to the analog comparator. The user can select interrupt triggering on comparator output
rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown
Figure 44. Analog Comparator Block Diagram
Analog Comparator Control
and Status Register – ACSR
Bit 7 – ACD: Analog Comparator Disable
When this bit is set (one), the power to the analog comparator is switched off. This bit
can be set at any time to turn off the analog comparator. This will reduce power con-
sumption in active and Idle mode. When changing the ACD bit, the Analog Comparator
interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise, an interrupt can
occur when the bit is changed.
Bit 6 – Res: Reserved Bit
This bit is a reserved bit in the ATmega103(L) and will always read as zero.
Bit 5 – ACO: Analog Comparator Output
ACO is directly connected to the comparator output.
Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined
by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit
is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when execut-
PE2
(AC+)
PE3
(AC-)
+
-
ACO
ACI
INTERRUPT
SELECT
ACIS1
ACIS0
ACIE
ACIC
ANALOG
COMPARATOR
IRQ
TO T/C1 CAPTURE
TRIGGER MUX
VCC
ACD
Bit
7654
321
0
$08 ($28)
ACD
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
ACSR
Read/Write
R/W
R
R/W
Initial Value
0
X
0
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