參數(shù)資料
型號: ATMEGA103-6AI
廠商: Atmel
文件頁數(shù): 106/141頁
文件大小: 0K
描述: IC MCU 128K 6MHZ A/D IT 64TQFP
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 90
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 6MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
配用: ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
67
ATmega103(L)
0945I–AVR–02/07
Figure 41. UART Transmitter
On the baud rate clock following the transfer operation to the Shift Register, the start bit
is shifted out on the TXD pin, followed by the data, LSB first. When the stop bit has been
shifted out, the Shift Register is loaded if any new data has been written to the UDR dur-
ing the transmission. During loading, UDRE is set. If there is no new data in the UDR
Register to send when the stop bit is shifted out, the UDRE Flag will remain set. In this
case, after the stop bit has been present on TXD for one bit length, the TX Complete
Flag (TXC) in USR is set.
The TXEN bit in UCR enables the UART Transmitter when set (one). When this bit is
cleared (zero), the PE1 pin can be used for general I/O. When TXEN is set, the UART
Transmitter will be connected to PE1, which is forced to be an output pin regardless of
the setting of the DDE1 bit in DDRE.
DATA BUS
UART I/O DATA
REGISTER (UDR)
10(11)-BIT TX
SHIFT REGISTER
UART CONTROL
REGISTER (UCR)
CONTROL LOGIC
UART STATUS
REGISTER (USR)
BAUD RATE
GENERATOR
XTAL
TXB8
RXB8
TXEN
CHR9
RXEN
TXC
TXCIE
RXCIE
UDRIE
UDRE
RXC
FE
OR
UDRE
/16
UDRE
IRQ
TXC
IRQ
SHIFT ENABLE
STORE UDR
1
IDLE
BAUD
BAUD x 16
PIN CONTROL
LOGIC
TXD
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