參數(shù)資料
型號(hào)： ATMEGA103-6AI
廠商： Atmel
文件頁數(shù)： 102/141頁
文件大?。?/td> 0K
描述： IC MCU 128K 6MHZ A/D IT 64TQFP
產(chǎn)品培訓(xùn)模塊： megaAVR Introduction
標(biāo)準(zhǔn)包裝： 90
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 6MHz
連通性： SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 128KB（64K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 托盤
配用： ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
63
ATmega103(L)
0945I–AVR–02/07
Bit 5 – DORD: Data Order
When the DORD bit is set (one), the LSB of the data word is transmitted first.
When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared
(zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be
cleared and SPIF in SPSR will become set. The user will then have to set MSTR to re-
enable SPI Master mode.
Bit 3 – CPOL: Clock Polarity
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is
low when idle. Refer to Figure 39 and Figure 40 for additional information.
Bit 2 – CPHA: Clock Phase
Refer to Figure 39 or Figure 40 for the functionality of this bit.
Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the CPU Clock
frequency (f
cl) is shown in Table 23.
Note:
Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL
divider is enabled.
SPI Status Register – SPSR
Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is gener-
ated if SPIE in SPCR is set (one) and Global Interrupts are enabled. SPIF is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively, the
SPIF bit is cleared by first reading the SPI Status Register with SPIF set (one), then
accessing the SPI Data Register (SPDR).
Bit 6 – WCOL: Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.
The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Reg-
ister with WCOL set (one), and then accessing the SPI Data Register.
Table 23. Relationship between SCK and the Oscillator Frequency
SPR1
SPR0
SCK Frequency
00
f
cl/4
01
f
cl/16
10
f
cl/64
11
f
cl/128
Bit
7654
321
0
$0E
SPIF
WCOL
–
SPSR
Read/Write
R
Initial Value
0000
000
0
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