參數(shù)資料
型號(hào): ATMEGA103-6AI
廠商: Atmel
文件頁數(shù): 107/141頁
文件大?。?/td> 0K
描述: IC MCU 128K 6MHZ A/D IT 64TQFP
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 90
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 6MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 128KB(64K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 4K x 8
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
配用: ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
68
ATmega103(L)
0945I–AVR–02/07
Data Reception
Figure 42. UART Receiver
The Receiver front-end logic samples the signal on the RXD pin at a frequency 16 times
the baud rate. While the line is idle, one single sample of logical “0” will be interpreted as
the falling edge of a start bit, and the start bit detection sequence is initiated. Let sample
1 denote the first zero-sample. Following the 1-to-0 transition, the Receiver samples the
RXD pin at samples 8, 9, and 10. If two or more of these three samples are found to be
logical “1”s, the start bit is rejected as a noise spike and the Receiver starts looking for
the next 1-to-0 transition.
If, however, a valid start bit is detected, sampling of the data bits following the start bit is
performed. These bits are also sampled at samples 8, 9 and 10. The logical value found
in at least two of the three samples is taken as the bit value. All bits are shifted into the
Transmitter Shift Register as they are sampled. Sampling of an incoming character is
shown in Figure 43.
DATA BUS
UART I/O DATA
REGISTER (UDR)
10(11)-BIT RX
SHIFT REGISTER
UART CONTROL
REGISTER (UCR)
DATA RECOVERY
LOGIC
UART STATUS
REGISTER (USR)
BAUD RATE
GENERATOR
XTAL
RXB8
TXB8
TXEN
CHR9
RXEN
TXC
TXCIE
RXCIE
UDRIE
UDRE
RXC
FE
DOR
RXC
IRQ
/16
BAUD X 16
BAUD
STORE UDR
PIN CONTROL
LOGIC
RXD
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