參數(shù)資料
型號(hào): AT43USB353M-AC
廠商: ATMEL CORP
元件分類(lèi): 微控制器/微處理器
英文描述: Low Cost Full-speed USB Microcontroller with Embedded Hub, ADC and PWM
中文描述: 8-BIT, MROM, 24 MHz, RISC MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MS-026BBC, LQFP-48
文件頁(yè)數(shù): 20/95頁(yè)
文件大?。?/td> 568K
代理商: AT43USB353M-AC
20
AT43USB353M
3307B–USB–4/04
Watchdog Timer
Reset
When the watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period t
TOUT
.
Figure 8.
Watchdog Reset During Operation
Non-USB Related
Interrupt Handling
The AT43USB353M has two non-USB 8-bit Interrupt Mask control registers; GIMSK (General
Interrupt Mask Register) and TIMSK (Timer/Counter Interrupt Mask Register).
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts
are disabled. The user software can set (one) the I-bit to enable nested interrupts. The I-bit is
set (one) when a Return from Interrupt instruction, RETI, is executed.
For Interrupts triggered by events that can remain static (e.g. the Output Compare register1
matching the value of Timer/Counter1) the interrupt flag is set when the event occurs. If the
interrupt flag is cleared and the interrupt condition persists, the flag will not be set until the
event occurs the next time.
When the Program Counter is vectored to the actual interrupt vector in order to execute the
interrupt handling routine, hard-ware clears the corresponding flag that generated the inter-
rupt. Some of the interrupt flags can also be cleared by writing a logic one to the flag bit
position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero),
the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero),
the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable
bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag, and will only be remembered for as long
as the interrupt condition is active.
t
TOUT
VCC
RESET
WDT
TIME-OUT
RESET
TIME-OUT
1 XTAL Cycle
INTERNAL
RESET
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