參數(shù)資料
型號(hào): AT43USB353M-AC
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: Low Cost Full-speed USB Microcontroller with Embedded Hub, ADC and PWM
中文描述: 8-BIT, MROM, 24 MHz, RISC MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MS-026BBC, LQFP-48
文件頁(yè)數(shù): 18/95頁(yè)
文件大?。?/td> 568K
代理商: AT43USB353M-AC
18
AT43USB353M
3307B–USB–4/04
Figure 5.
AT43USB353M Interrupt Structure
Reset Sources
The AT43USB353M has four sources of reset:
Power-on Reset
– The MCU is reset when the supply voltage is below the power-on reset
threshold.
External Reset
– The MCU is reset when a low level is present on the RESETN pin for
more than 50 ns.
Watchdog Reset
– The MCU is reset when the watchdog timer period expires and the
watchdog is enabled.
USB Reset
– The AT43USB353M has a feature to separate the USB and microcontroller
resets. This feature is enabled by setting the BUS INT EN, bit 3 of the SPRSIE register. A
USB bus reset is defined as a SE0 (single ended zero) of at least 4 slow speed USB clock
cycles received by Port0. The internal reset pulse to the USB hardware and
microcontroller lasts for 24 oscillator periods.
Resets not separated: A USB bus reset will also reset the microcontroller.
Separated reset: A USB bus reset will only reset the USB hardware, while an
interrupt to the microcontroller will be generated if the BUS INT MSK bit, bit 3 of
SPRSMSK register, is also set.
When the USB hardware is reset, the compound device is de-configured and has to be re-
enumerated by the host. When the microcontroller is reset, all I/O registers are then set to their
initial values, and the program starts execution from address $000. The instruction placed in
Suspend/Resume
Register
Suspend/Resume
Interrupt Enable
Register
Suspend/Resume
Interrupt Mask
Register
USB Interrupt
Flag Register
USB Interrupt
Enable Register
USB Interrupt
Mask Register
USB
ADC
TIMER0 OVF
TIMER1 OVF
TIMER1 COMPB
TIMER1 COMPA
TIMER1CAPT
INT1
INT0
RESET
Microcontroller
Interrupt
Logic
13
12
8
7
6
5
4
3
2
1
SOF
EOF2
FEP3
FEP2
FEP1
FEP0
RESERVED
HEP0
FRMWUP
RSM
GLB SUSP
BUS RESET
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