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參數(shù)資料
| 型號(hào)： | ASM5I9772AG-52-ER |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| 中文描述： | 200 MHz, OTHER CLOCK GENERATOR, PQFP52 |
| 封裝： | GREEN, TQFP-52 |
| 文件頁(yè)數(shù)： | 9/15頁(yè) |
| 文件大?。?/td> | 583K |
| 代理商： | ASM5I9772AG-52-ER |
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June 2005
rev 0.3
AC Parameters
(VDD= 3.3V ± 5%, T
A
= –40°C to +85°C) (Continued)
6
Parameter
Description
ASM5I9772A
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
9 of 15
Notice: The information in this document is subject to change without notice.
Condition
Min
-
Typ
-
Max
150
Unit
Skew within Bank C
t
sk(B)
t
PLZ, HZ
t
PZL, ZH
Bank-to-Bank Skew
-
-
325
pS
Output Disable Time
-
-
8
nS
Output Enable Time
-
-
8
nS
÷4 Feedback
-
1.3 - 2.0
-
÷6 Feedback
-
0.7 - 1.3
-
÷8 Feedback
-
0.9 - 1.3
-
÷10 Feedback
-
0.6 - 1.1
-
÷12 Feedback
-
0.6 - 0.9
-
÷16 Feedback
-
0.4 - 0.6
-
BW
PLL Closed-Loop Bandwidth
(–3 dB)
÷20 Feedback
Same frequency (125 MHz)
RMS (1
σ
)
-
0.6 - 0.9
-
MHz
-
7
30
Same frequency
-
-
100
t
JIT(CC)
Cycle-to-Cycle Jitter
Multiple frequencies
-
-
375
pS
Same frequency (125 MHz)
RMS (1
σ
)
Same frequency
-
6
30
-
45
75
t
JIT(PER)
Period Jitter
Multiple frequencies
-
-
225
pS
t
JIT(
φ
)
t
LOCK
I/O Phase Jitter
I/O same VDD
-
-
150
pS
Maximum PLL Lock Time
-
-
1
mS
Sync Output
In situations where output frequency relationships are not
integer multiples of each other, the SYNC output provides a
signal for system synchronization. The ASM5I9772A
monitors the relationship between the QA and the QC
output clocks. It provides a low going pulse, one period in
duration, one period prior to the coincident rising edges of
the QA and QC outputs.
The duration and the placement of the pulse depend on the
higher of the QA and QC output frequencies. The following
timing diagram illustrates various waveforms for the SYNC
output. Note that the SYNC output is defined for all
possible combinations of the QA and QC outputs even
though under some relationships the lower frequency clock
could be used as a synchronizing signal.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9772AG-52-ET | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A-52-ER | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A-52-ET | Octal D-Type Flip-Flops With Clear 20-SOIC -40 to 85 |
| ASM5I9773AG-52-ER | Octal D-Type Flip-Flops With Clear 20-SOIC -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9772AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
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