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參數(shù)資料
| 型號(hào)： | ASM5I9772AG-52-ER |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| 中文描述： | 200 MHz, OTHER CLOCK GENERATOR, PQFP52 |
| 封裝： | GREEN, TQFP-52 |
| 文件頁數(shù)： | 7/15頁 |
| 文件大小： | 583K |
| 代理商： | ASM5I9772AG-52-ER |
June 2005
rev 0.3
ASM5I9772A
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
7 of 15
Notice: The information in this document is subject to change without notice.
AC Electrical Specifications
(VDD = 2.5V ± 5%, T
A
= –40°C to +85°C)
1
Parameter
Description
Condition
Min
Typ
Max
Unit
f
VCO
f
XTAL
VCO Frequency
Crystal Frequency Range
see Table 7
÷4 Feedback
÷6 Feedback
÷8 Feedback
÷10 Feedback
÷12 Feedback
÷16 Feedback
÷20 Feedback
÷24 Feedback
÷32 Feedback
÷40 Feedback
Bypass mode
(PLL_EN = 0)
0.7V to 1.7V
÷2 Output
÷4 Output
÷6 Output
÷8 Output
÷10 Output
÷12 Output
÷16 Output
÷20 Output
÷24 Output
fMAX < 100 MHz
fMAX > 100 MHz
0.6V to 1.8V
200
10
50
33.3
25
20
16.6
12.5
10
8.3
6.25
5
-
-
-
-
-
-
-
-
-
-
-
-
380
25
95
63.3
47.5
38
31.6
23.75
19
15.8
11.8
9.5
MHz
MHz
f
in
Input Frequency
0
-
200
MHz
f
refDC
t
r
, t
f
Input Duty Cycle
TCLK Input Rise/FallTime
25
-
100
50
33.3
25
20
16.6
12.5
10
8.3
-
47.5
45
0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
75
1.0
190
95
63.3
47.5
38
31.6
23.75
19
15.8
20
52.5
55
1.0
%
nS
f
MAX
Maximum Output Frequency
MHz
f
SCLK
Serial Clock Frequency
MHz
DC
Output Duty Cycle
%
t
r
, t
f
Output Rise/Fall times
Propagation Delay
(static phase offset)
nS
t
(
φ
)
TCLK to FB_IN
-125
-
125
pS
Skew within Bank A
Skew within Bank B
Skew within Bank C
÷4 Feedback
÷6 Feedback
÷8 Feedback
÷10 Feedback
÷12 Feedback
÷16 Feedback
÷20 Feedback
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
75
100
150
400
10
10
-
-
-
-
-
-
-
t
sk(O)
Output-to-Output Skew
pS
t
sk(B)
t
PLZ, HZ
t
PZL, ZH
Bank-to-Bank Skew
Output Disable Time
Output Enable Time
pS
nS
nS
1.3–2.0
0.7–1.3
0.9–1.3
0.6–1.1
0.6–0.9
0.4–0.6
0.6–0.9
BW
PLL Closed Loop Bandwidth
(–3 dB)
MHz
Note: 1. AC characteristics apply for parallel output termination of 50
to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are
guaranteed by characterization and are not 100% tested.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9772AG-52-ET | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A-52-ER | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A-52-ET | Octal D-Type Flip-Flops With Clear 20-SOIC -40 to 85 |
| ASM5I9773AG-52-ER | Octal D-Type Flip-Flops With Clear 20-SOIC -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9772AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
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