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參數(shù)資料
| 型號： | ASM5I9772AG-52-ER |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| 中文描述： | 200 MHz, OTHER CLOCK GENERATOR, PQFP52 |
| 封裝： | GREEN, TQFP-52 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 583K |
| 代理商： | ASM5I9772AG-52-ER |
June 2005
rev 0.3
ASM5I9772A
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
11 of 15
Notice: The information in this document is subject to change without notice.
Figure 2.
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
Table 7. Suggested Oscillator Crystal Parameters
Parameter
Description
Conditions
Min
Typ
Max
Unit
T
C
Frequency Tolerance
–
–
±1100
PPM
T
S
Frequency Temperature Stability
(T
A
–10° to +60°C)
–
–
± 100
PPM
T
A
Aging
(First three years @ 25°C)
–
–
5
PPM/Yr
C
L
Load Capacitance
Effective Series Resistance
(ESR)
The crystal’s rated load
–
20
–
pF
R
ESR
–
40
80
Ohm
Figure 3. LVCMOS_CLK AC Test Reference for VDD = 3.3V/2.5V
Figure 4. LVCMOS Propagation Delay t(
φ
), Static Phase Offset
D0 D1 D2
D3
D4
D5
D6
D7
D8
D9 D10 D11
Start
Bit
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
R
T
= 50 ohm
VTT
VTT
LVCMOS_CLK
VDD
VDD
VDD/2
VDD/2
GND
GND
t(
φ
)
FB_IN
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ASM5I9772AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
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