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參數(shù)資料
| 型號： | ASM5I9772AG-52-ER |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| 中文描述： | 200 MHz, OTHER CLOCK GENERATOR, PQFP52 |
| 封裝： | GREEN, TQFP-52 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大小： | 583K |
| 代理商： | ASM5I9772AG-52-ER |
June 2005
rev 0.3
AC Electrical Specifications
(VDD
= 2.5V ± 5%, T
A
= –40°C to +85°C) (Continued)
6
Parameter
Description
t
JIT(CC)
Cycle-to-Cycle Jitter
ASM5I9772A
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
8 of 15
Notice: The information in this document is subject to change without notice.
Condition
Min
-
Typ
7
Max
30
Unit
pS
Same frequency (125 MHz)
RMS (1
σ
)
Same frequency
Multiple frequencies
Same frequency (125 MHz)
RMS (1
σ
)
Same frequency
Multiple frequencies
-
-
-
-
-
6
150
435
30
-
-
-
-
45
-
-
-
75
235
150
1
t
JIT(PER)
Period Jitter
pS
t
JIT(
φ
)
t
LOCK
I/O Phase Jitter
Maximum PLL Lock Time
pS
mS
AC Parameters
(VDD= 3.3V ± 5%, TA= –40°C to +85°C)
6
Parameter
Description
f
VCO
VCO Frequency
f
XTAL
Crystal Frequency Range
Condition
Min
200
10
50
33.3
25
20
16.6
12.5
10
8.3
6.25
5
0
25
-
100
50
33.3
25
20
16.6
12.5
10
8.3
-
48
45
0.1
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
500
25
125
83.3
62.5
50
41.6
31.25
25
20.8
15.625
12.5
200
75
1.0
200
125
83.3
62.5
50
41.6
31.25
25
20.8
20
52
55
1.0
Unit
MHz
MHz
see Table 7
÷4 Feedback
÷6 Feedback
÷8 Feedback
÷10 Feedback
÷12 Feedback
÷16 Feedback
÷20 Feedback
÷24 Feedback
÷32 Feedback
÷40 Feedback
Bypass mode (PLL_EN = 0)
0.8V to 2.0V
÷2 Output
÷4 Output
÷6 Output
÷8 Output
÷10 Output
÷12 Output
÷16 Output
÷20 Output
÷24 Output
f
MAX
< 100 MHz
f
MAX
> 100 MHz
0.55V to 2.4V
f
in
Input Frequency
MHz
f
refDC
t
r
, t
f
Input Duty Cycle
TCLK Input Rise/FallTime
%
nS
f
MAX
Maximum Output Frequency
MHz
f
MAX
Maximum Output Frequency
(continued)
MHz
f
SCLK
Serial Clock Frequency
MHz
DC
Output Duty Cycle
%
t
r
, t
f
Output Rise/Fall times
Propagation Delay (static
phase offset)
nS
t
(
φ
)
TCLK to FB_IN, same VDD
-125
-
125
pS
Skew within Bank A
Skew within Bank B
-
-
-
-
75
100
t
sk(O)
Output-to-Output Skew
pS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9772AG-52-ET | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A-52-ER | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A-52-ET | Octal D-Type Flip-Flops With Clear 20-SOIC -40 to 85 |
| ASM5I9773AG-52-ER | Octal D-Type Flip-Flops With Clear 20-SOIC -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9772AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
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