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參數(shù)資料
| 型號(hào)： | AS7C513C |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 5 V 32K X 16 CMOS SRAM |
| 中文描述： | 5伏32K的× 16 CMOS SRAM的 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 145K |
| 代理商： | AS7C513C |
AS7C513C
12/5/06, v 1.0
Alliance Memory
P. 6 of 9
Write waveform 2 (CE controlled)
11
AC test conditions
– Output load: see Figure B.
– Input pulse level: GND to 3.0 V. See Figure A.
– Input rise and fall times: 3 ns. See Figure A.
– Input and output timing reference levels: 1.5
Notes:
1
2
3
4
5
6
7
8
9
10 N/A.
11
All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions
, Figures A and B.
These parameters are specified with C
L
= 5 pF, as in Figures B. Transition is measured ± 200 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is high for read cycle.
CE and OE are low for read cycle.
Address is valid prior to or coincident with CE transition low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
Address
CE
LB, UB
WE
Data
IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
OW
t
WZ
t
WR
Data
OUT
Data undefined
high Z
high Z
t
AS
t
AW
Data valid
t
CLZ
t
AH
168
Ω
Thevenin Equivalent:
D
OUT
+1.728 V
255
Ω
C
13
480
Ω
GND
+5 V
Figure B: 5 V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
3 ns
D
OUT
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