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參數(shù)資料
| 型號： | AS7C513C |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 5 V 32K X 16 CMOS SRAM |
| 中文描述： | 5伏32K的× 16 CMOS SRAM的 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 145K |
| 代理商： | AS7C513C |
September 2006
Advance Information
Copyright Alliance Memory. All rights reserved.
AS7C513C
5 V 32K X 16 CMOS SRAM
12/5/06, v 1.0
Alliance Memory
P. 1 of 9
Features
Industrial (-40
o
to 85
o
C) temperature
Organization: 32,768 words × 16 bits
Center power and ground pins for low noise
High speed
- 12 ns address access time
- 6 ns output enable access time
Low power consumption via chip deselect
Easy memory expansion with
CE
,
OE
inputs
TTL-compatible, three-state I/O
Upper and Lower byte pin
JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin TSOP 2
ESD protection
≥
2000 volts
Logic block diagram
32,768 x 16
Array
OE
LB
CE
WE
Address decoder
A
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A
A
A
A
A
A
A
Control circuit
I/O0–I/O7
I/O8–I/O15
UB
I/O
buffer
Pin arrangement
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
I/O13
I/O12
GND
V
I/O11
I/O10
I/O9
I/O8
NC
A7
A8
A9
A10
NC
A0
CE
I/O0
I/O1
I/O2
I/O3
V
CC
GND
I/O4
I/O5
I/O6
I/O7
WE
A14
A13
A12
A11
NC
44-Pin SOJ (400 mil), TSOP 2
UB
LB
I/O15
I/O14
2
3
4
A3
A2
A1
1
NC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A5
A6
OE
A4
A
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