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參數(shù)資料
| 型號(hào)： | AS7C513C |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 5 V 32K X 16 CMOS SRAM |
| 中文描述： | 5伏32K的× 16 CMOS SRAM的 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 145K |
| 代理商： | AS7C513C |
AS7C513C
12/5/06, v 1.0
Alliance Memory
P. 4 of 9
Key to switching waveforms
Read waveform 1 (address controlled)
3,6,7,9
Read waveform 2 (OE, CE, UB, LB controlled)
3,6,8,9
Read cycle (over the operating range)
3,9
Parameter
Symbol
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
BA
t
BLZ
t
BHZ
t
OHZ
t
PU
t
PD
AS7C513C-12
Min
12
–
–
–
4
4
–
0
–
0
–
–
0
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Max
–
12
12
7
–
–
6
–
7
–
6
6
–
12
Read cycle time
Address access time
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE low to output in low Z
CE high to output in high Z
OE low to output in low Z
Byte select access time
Byte select Low to low Z
Byte select High to high Z
OE high to output in high Z
Power up time
Power down time
3
3
5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
Undefined output/don’t care
Falling input
Rising input
t
OH
t
AA
t
RC
t
OH
Data
OUT
Address
Data valid
Previous data valid
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
HZ
t
BHZ
t
ACE
t
LZ
Address
OE
CE
LB, UB
Data
IN
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