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參數(shù)資料
| 型號： | AS7C25512PFS32A-225BC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 32 STANDARD SRAM, 6.9 ns, PBGA165 |
| 封裝： | BGA-165 |
| 文件頁數(shù)： | 20/21頁 |
| 文件大?。?/td> | 458K |
| 代理商： | AS7C25512PFS32A-225BC |
AS7C25512PFS32A
AS7C25512PFS36A
12/2/02, v. 0.9.1
Alliance Semiconductor
8 of 21
Timing characteristics over operating range
Parameter
Sym
–250
–225
–200
–166
Unit
Notes1
1
Min
Max
Min
Max
Min
Max
Min
Max
Clock frequency
fMax
–
250
–
225
–
200
–
166
MHz
Cycle time (pipelined mode)
tCYC
4–
4.4
–
5–6–
ns
Cycle time (flow-through mode)
tCYCF
6.5
–
6.9
–
7.5
–
8.5
–
ns
Clock access time (pipelined mode)
tCD
–
2.6
–
2.8
–
3.0
–
3.4
ns
Clock access time (flow-through
mode)
tCDF
–
6.5
–
6.9
–
7.5
–
8.5
ns
Output enable low to data valid
tOE
–
2.6
–
2.8
–
3.0
–
3.4
ns
Clock high to output low Z
tLZC
0
–
0
–
0
–
0
–
ns
2,3,4
Data output invalid from clock high
tOH
1.5
–
1.5
–
1.5
–
1.5
–
ns
2
Output enable low to output low Z
tLZOE
0
–
0
–
0
–
0
–
ns
2,3,4
Output enable high to output high Z
tHZOE
–
2.6
–
2.8
–
3.0
–
3.4
ns
2,3,4
Clock high to output high Z
tHZC
–
2.6
–
2.8
–
3.0
–
3.4
ns
2,3,4
Output enable high to invalid output
tOHOE
0–0
–
0–0–
ns
Clock high pulse width
tCH
1.5
–
1.8
–
1.8
–
2.1
–
ns
5
Clock low pulse width
tCL
1.5
–
1.8
–
1.8
–
2.2
–
ns
5
Address setup to clock high
tAS
1.2
–
1.4
–
1.4
–
1.5
–
ns
6
Data setup to clock high
tDS
1.2
–
1.4
–
1.4
–
1.5
–
ns
6
Write setup to clock high
tWS
1.2
–
1.4
–
1.4
–
1.5
–
ns
6,7
Chip select setup to clock high
tCSS
1.2
–
1.4
–
1.4
–
1.5
–
ns
6,8
Address hold from clock high
tAH
0.3
–
0.4
–
0.4
–
0.5
–
ns
6
Data hold from clock high
tDH
0.3
–
0.4
–
0.4
–
0.5
–
ns
6
Write hold from clock high
tWH
0.3
–
0.4
–
0.4
–
0.5
–
ns
6,7
Chip select hold from clock high
tCSH
0.3
–
0.4
–
0.4
–
0.5
–
ns
6,8
ADV setup to clock high
tADVS
1.2
–
1.4
–
1.4
–
1.5
–
ns
6
ADSP setup to clock high
tADSPS
1.2
–
1.4
–
1.4
–
1.5
–
ns
6
ADSC setup to clock high
tADSCS
1.2
–
1.4
–
1.4
–
1.5
–
ns
6
ADV hold from clock high
tADVH
0.3
–
0.4
–
0.4
–
0.5
–
ns
6
ADSP hold from clock high
tADSPH
0.3
–
0.4
–
0.4
–
0.5
–
ns
6
ADSC hold from clock high
tADSCH
0.3
–
0.4
–
0.4
–
0.5
–
ns
6
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C25512PFS36A-133TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C25512PFS36A-133TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C25512PFS36A-133TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C25512PFS36A-133TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C25512PFS36A-166TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512K x 32/36 pipelined burst synchronous SRAM |
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