參數(shù)資料
型號(hào)： AS7C25512PFS32A-225BC
廠商： ALLIANCE SEMICONDUCTOR CORP
元件分類(lèi)： SRAM
英文描述： 512K X 32 STANDARD SRAM, 6.9 ns, PBGA165
封裝： BGA-165
文件頁(yè)數(shù)： 15/21頁(yè)
文件大?。?/td> 458K
代理商： AS7C25512PFS32A-225BC
12/2/02, v. 0.9.1
Alliance Semiconductor
3 of 21
AS7C25512PFS32A
AS7C25512PFS36A
Functional description
The AS7C25512PFS32A/36A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as
524,288 words x 32/36. It incorporates a two-stage register-register pipeline for highest frequency on any given technology.
Fast cycle times of 4/4.4/5/6 ns with clock access times (tCD) of 2.6/2.8/3/3.4 ns enable 250, 225, 200, and 166 MHz bus frequencies.
Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe
(ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data accessed
by the current address registered in the address registers by the positive edge of CLK are carried to the data-out registers and driven on the
output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent
clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high.
Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved count sequence. With
LBO driven low, the device uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/
36 regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE
and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled lOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented internally
to the next burst address if BWn and ADV are sampled low. This device operates in single-cycle deselect feature during read cycles.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C33512PFS32A/36A family operates from a core 2.5V power supply. These devices are available in a 100-pin TQFP and 165-ball BGA.
TQFP and BGA capacitance
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
CIN
Address and control pins
VIN = 0V
5
pF
I/O capacitance
CI/O
I/O pins
VOUT = 0V
7
pF
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS7C25512PFS36A-133TQC 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:2.5V 512K x 32/36 pipelined burst synchronous SRAM
AS7C25512PFS36A-133TQCN 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:2.5V 512K x 32/36 pipelined burst synchronous SRAM
AS7C25512PFS36A-133TQI 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:2.5V 512K x 32/36 pipelined burst synchronous SRAM
AS7C25512PFS36A-133TQIN 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:2.5V 512K x 32/36 pipelined burst synchronous SRAM
AS7C25512PFS36A-166TQC 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:2.5V 512K x 32/36 pipelined burst synchronous SRAM
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