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參數(shù)資料
| 型號： | AS6WA25616 |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 3.0V to 3.6V 256K×16 Intelliwatt low-power CMOS SRAM with one chip enable(3.0V 到 3.6V 256K×16 Intelliwatt 低功耗 CMOS 靜態(tài)RAM（帶單片使能）) |
| 中文描述： | 3.0V至3.6V 256K × 16 Intelliwatt低功耗CMOS SRAM的同一個芯片上，使（3.0V到3.6V的256K × 16 Intelliwatt低功耗的CMOS靜態(tài)隨機存儲器（帶單片使能）） |
| 文件頁數(shù)： | 6/9頁 |
| 文件大小： | 180K |
| 代理商： | AS6WA25616 |
6
ALLIANCE SEMICONDUCTOR
10/6/00
AS6WA25616
Data retention characteristics (over the operating range)
13,5
Parameter
V
CC
for data retention
Data retention current
Data retention waveform
AC test loads and waveforms
Notes
1
2
3
4
5
6
7
8
9
10 CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A.
13 1.2V data retention applies to commercial and industrial temperature range operations.
14 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
During V
CC
power-up, a pull-up resistor to V
CC
on CS is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions
.
t
CLZ
and t
CHZ
are specified with C
L
= 5pF as in Figure C. Transition is measured
±
500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CS and OE are LOW for read cycle.
Address valid prior to or coincident with CS transition LOW.
All read cycle timings are referenced from the last valid address to the first transitioning address.
Symbol
V
DR
I
CCDR
t
CDR
t
R
Test conditions
V
CC
= 1.2V
CS
≥
V
CC
– 0.1V or
UB = LB = > V
CC
– 0.1V
V
IN
≥
V
CC
– 0.1V or
V
IN
≤
0.1V
Min
1.2V
Max
3.6
Unit
V
μ
A
ns
ns
–
4
Chip deselect to data retention time
Operation recovery time
0
–
–
t
RC
Parameters
V
CC
= 3.0V
1105
V
CC
= 2.5V
16670
V
CC
= 2.0V
15294
Unit
R1
Ohms
R2
R
TH
V
TH
1550
645
15380
8000
11300
6500
Ohms
Ohms
1.75V
1.2V
0.85V
Volts
V
CC
CS
t
R
t
CDR
Data retention mode
V
CC
V
CC
V
DR
≥
1.2V
V
IH
V
IH
V
DR
V
CC
R1
R2
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
V
CC
R1
R2
OUTPUT
5 pF
ALL INPUT PULSES
(b)
10%
90%
10%
90%
GND
V
CC
Typ
< 5 ns
(c)
Thevenin equivalent:
OUTPUT
R
TH
V
INCLUDING
JIG AND
SCOPE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS6WA25616-BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3.0V to 3.6V 256K?6 IntelliwattTM low-power CMOS SRAM with one chip enable |
| AS6WA25616-BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3.0V to 3.6V 256K?6 IntelliwattTM low-power CMOS SRAM with one chip enable |
| AS6WA25616-TC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3.0V to 3.6V 256K?6 IntelliwattTM low-power CMOS SRAM with one chip enable |
| AS6WA25616-TI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3.0V to 3.6V 256K X 6 IntelliwattTM low-power CMOS SRAM with one chip enable |
| AS6WA5128 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.0V to 3.6V 512K 】 8 Intelliwatt low-power CMOS SRAM |
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