參數(shù)資料
型號(hào): AS6WA25616
廠商: Alliance Semiconductor Corporation
英文描述: 3.0V to 3.6V 256K×16 Intelliwatt low-power CMOS SRAM with one chip enable(3.0V 到 3.6V 256K×16 Intelliwatt 低功耗 CMOS 靜態(tài)RAM(帶單片使能))
中文描述: 3.0V至3.6V 256K × 16 Intelliwatt低功耗CMOS SRAM的同一個(gè)芯片上,使(3.0V到3.6V的256K × 16 Intelliwatt低功耗的CMOS靜態(tài)隨機(jī)存儲(chǔ)器(帶單片使能))
文件頁(yè)數(shù): 4/9頁(yè)
文件大小: 180K
代理商: AS6WA25616
4
ALLIANCE SEMICONDUCTOR
10/6/00
AS6WA25616
Read cycle (over the operating range)
3,9
Parameter
Read cycle time
Shaded areas indicate preliminary information.
Key to switching waveforms
Read waveform 1 (address controlled)
3,6,7,9
Read waveform 2 (CS, OE, UB, LB controlled)
3,6,8,9
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
BA
t
BLZ
t
BHZ
t
OHZ
t
PU
t
PD
Min
55
Max
Unit
ns
Notes
Address access time
55
ns
3
Chip select (CS) access time
Output enable (OE) access time
55
25
ns
ns
3
Output hold from address change
10
ns
5
CS low to output in low Z
CS high to output in high Z
10
0
20
ns
ns
4, 5
4, 5
OE low to output in low Z
5
ns
4, 5
UB/LB access time
UB/LB low to low Z
10
55
ns
ns
4, 5
UB/LB high to high Z
0
20
ns
4, 5
OE high to output in high Z
Power up time
0
0
20
ns
ns
4, 5
4, 5
Power down time
55
ns
4, 5
Undefined/don’t care
Falling input
Rising input
t
OH
t
AA
t
RC
t
OH
D
OUT
Address
Data valid
Previous data valid
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
HZ
t
BHZ
t
ACS
t
LZ
Address
OE
CS
LB, UB
D
OUT
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