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參數(shù)資料
| 型號(hào)： | AS6WA25616 |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 3.0V to 3.6V 256K×16 Intelliwatt low-power CMOS SRAM with one chip enable(3.0V 到 3.6V 256K×16 Intelliwatt 低功耗 CMOS 靜態(tài)RAM（帶單片使能）) |
| 中文描述： | 3.0V至3.6V 256K × 16 Intelliwatt低功耗CMOS SRAM的同一個(gè)芯片上，使（3.0V到3.6V的256K × 16 Intelliwatt低功耗的CMOS靜態(tài)隨機(jī)存儲(chǔ)器（帶單片使能）） |
| 文件頁(yè)數(shù)： | 2/9頁(yè) |
| 文件大小： | 180K |
| 代理商： | AS6WA25616 |
2
ALLIANCE SEMICONDUCTOR
10/6/00
AS6WA25616
Functional description
The AS6WA25616 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words × 16
bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 55 ns are ideal for low-power applications. Active high and low chip selects ( CS)
permit easy memory expansion with multiple-bank memory systems.
When CS is high, or UB and LB are high, the device enters standby mode: the AS6WA25616 is guaranteed not to exceed 72
μ
W power
consumption at 3.6V and 55 ns. The device also returns data when V
CC
is reduced to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and chip select (CS) low, and UB and/or LB low. Data on the input pins
I/O1–O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip select (CS), UB and LB low, with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write enable is
active, or (UB) and (LB), output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written
and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 3.0 to 3.6V supply. Device is available in the JEDEC
standard
400-mm, TSOP II, and 48-ball FBGA packages.
Absolute maximum ratings
Note: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don’t care, L = Low, H = High.
Parameter
Device
Symbol
Min
Max
Unit
Voltage on V
CC
relative to V
SS
Voltage on any I/O pin relative to GND
V
tIN
V
tI/O
P
D
T
stg
T
bias
I
OUT
–0.5
–0.5
V
CC
+ 0.5
V
V
Power dissipation
–
1.0
W
°
C
°
C
mA
Storage temperature (plastic)
Temperature with V
CC
applied
DC output current (low)
–65
–55
+150
+125
–
20
CS
H
WE
X
OE
X
LB
X
UB
X
Supply
Current
I/O1–I/O8
I/O9–I/O16
Mode
I
SB
High Z
High Z
Standby (I
SB
)
L
X
X
H
H
L
H
H
X
L
X
H
I
CC
High Z
D
OUT
High Z
High Z
High Z
Output disable (I
CC
)
L
H
L
I
CC
Read (I
CC
)
H
L
D
OUT
D
OUT
High Z
L
L
L
H
D
OUT
D
IN
High Z
L
L
X
I
CC
Write (I
CC
)
H
L
D
IN
D
IN
L
L
D
IN
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS6WA25616-BC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:3.0V to 3.6V 256K?6 IntelliwattTM low-power CMOS SRAM with one chip enable |
| AS6WA25616-BI | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:3.0V to 3.6V 256K?6 IntelliwattTM low-power CMOS SRAM with one chip enable |
| AS6WA25616-TC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:3.0V to 3.6V 256K?6 IntelliwattTM low-power CMOS SRAM with one chip enable |
| AS6WA25616-TI | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:3.0V to 3.6V 256K X 6 IntelliwattTM low-power CMOS SRAM with one chip enable |
| AS6WA5128 | 制造商:ALSC 制造商全稱(chēng):Alliance Semiconductor Corporation 功能描述:3.0V to 3.6V 512K 】 8 Intelliwatt low-power CMOS SRAM |
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