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參數(shù)資料
| 型號： | AS4SD16M16 |
| 英文描述： | 256000Kbits 16M x 16 Replacement with DSCC 5962-n/a | SDRAM |
| 中文描述： | 256000Kbits 16米x 16置換籍局5962氮/ 1 |內(nèi)存 |
| 文件頁數(shù)： | 9/51頁 |
| 文件大?。?/td> | 1071K |
| 代理商： | AS4SD16M16 |
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S DR A M
AS4SD16M16
Austin Semiconductor, Inc.
AS4SD16M16
Rev. 1.5 6/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
OPERATION
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to a
bank within the SDRAM, a row in that bank must be “opened.”
This is accomplished via the ACTIVE command, which selects
both the bank and the row to be activated (see Figure 3).
After opening a row (issuing an ACTIVE command), a
READ or WRITE command may be issued to that row, subject
to the t
RCD
specification. t
RCD
(MIN) should be divided by the
clock period and rounded up to the next whole number to
determine the earliest clock edge after the ACTIVE command
on which a READ or WRITE command can be entered. For
example, a tRCD specification of 20ns with a 125 MHz clock
(8ns period) results in 2.5 clocks, rounded to 3. This is reflected
in Figure 4, which covers any case where 2 < t
RCD
(MIN)/
t
CK
< 3. (The same procedure is used to convert other specifi-
cation limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active row has
been “closed” (precharged). The minimum time interval
between successive ACTIVE commands to the same bank is
defined by t
RC
.
A subsequent ACTIVE command to another bank can be
issued while the first bank is being accessed, which results in a
reduction of total row-access overhead. The minimum time
interval between successive ACTIVE commands to different
banks is defined by t
RRD
.
FIGURE 3: Activating a Specific
Row in a Specific Bank
FIGURE 4: Example - Meeting t
RCD
(MIN) When 2 < t
RCD
(MIN)/ t
CK
< 3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS4SD1M16S-10 | x16 SDRAM |
| AS4SD1M16S-12 | x16 SDRAM |
| AS4SD1M16S-8A | x16 SDRAM |
| AS4SD4M16A2-10 | x16 SDRAM |
| AS4SD4M16A2-8 | x16 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4SD16M16_09 | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:256 MB: 16 Meg x 16 SDRAM Synchronous DRAM Memory |
| AS4SD16M16DG-75 | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:256 MB: 16 Meg x 16 SDRAM Synchronous DRAM Memory |
| AS4SD16M16DG-75/ET | 制造商:Micross Components 功能描述:SDRAM-SDR,256MB - Trays |
| AS4SD16M16DG-75/IT | 制造商:Micross Components 功能描述:SDRAM-SDR,256MB - Trays |
| AS4SD16M16DG-75/IT+ | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:256 MB: 16 Meg x 16 SDRAM Synchronous DRAM Memory |
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