參數(shù)資料
型號: AS4SD4M16A2-10
英文描述: x16 SDRAM
中文描述: x16內(nèi)存
文件頁數(shù): 1/51頁
文件大?。?/td> 1071K
代理商: AS4SD4M16A2-10
S DR A M
AS4SD16M16
Austin Semiconductor, Inc.
AS4SD16M16
Rev. 1.5 6/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
FEATURES
Full Military temp (-55°C to 125°C) processing available
Configuration: 16 Meg x 16 (4 Meg x 16 x 4 banks)
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8 or full page
Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
Self Refresh Mode (IT)
64ms, 8,192-cycle refresh (IT)
<24ms 8,192 cycle recfresh (XT)
WRITE Recovery (t
WR
= “2 CLK”)
LVTTL-compatible inputs and outputs
Single +3.3V ±0.3V power supply
OPTIONS
Plastic Package - OCPL*
54-pin TSOP (400 mil) DG No. 901
MARKING
Timing (Cycle Time)
7.5ns @ CL = 3 (PC133) or
7.5ns @ CL = 2 (PC100)
-75
Operating Temperature Ranges
-Industrial Temp (-40°C to 85° C) IT
-Industrial Plus Temp
(-45°C to +105°C)
IT+
-Military Temp (-55°C to 125°C) XT***
*Off-center parting line
**CL = CAS (READ) latency
***Consult Factory
PIN ASSIGNMENT
(Top View)
54-Pin TSOP
Note: “\” indicates an active low.
256 MB: 16 Meg x 16 SDRAM
Synchronous DRAM Memory
For more products and information
please visit our web site at
www.austinsemiconductor.com
KEY TIMING PARAMETERS
SPEED
GRADE
-75
-75
CLOCK
FREQUENCY CL = 2**
133 MHz
100 MHz
SETUP
TIME
1.5ns
1.5ns
HOLD
TIME
0.8ns
0.8ns
CL = 3**
5.4ns
6ns
ACCESS TIME
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
4 Meg x 16 x 4 banks
8K
8K (A0-A12)
4 (BA0, BA1)
512 (A0-A8)
16 Meg x 16
相關PDF資料
PDF描述
AS4SD4M16A2-8 x16 SDRAM
AS5010 Voltage Reference
AS5010GN Voltage Reference
AS5010HN Voltage Reference
AS5010JT Voltage Reference
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