參數(shù)資料
型號(hào)： AS4SD4M16A2-10
英文描述： x16 SDRAM
中文描述： x16內(nèi)存
文件頁(yè)數(shù)： 7/51頁(yè)
文件大?。?/td> 1071K
代理商： AS4SD4M16A2-10
S DR A M
AS4SD16M16
Austin Semiconductor, Inc.
AS4SD16M16
Rev. 1.5 6/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
COMMANDS
Truth Table 1 provides a quick reference of available
commands. This is followed by a written description of each
command. Three additional Truth Tables appear following the
Operation section; these tables provide current state/next state
information.
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new
commands from being executed by the SDRAM, regardless of
whether the CLK signal is enabled. The SDRAM is effectively
deselected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a
NOP to an SDRAM which is selected (CS\ is LOW). This
prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not
affected.
LOAD MODE REGISTER
The mode register is loaded via inputs A0-A11 (A12 should be
driven LOW). See mode register heading in the Register Defini-
tion section. The LOAD MODE REGISTER command can only
be issued when all banks are idle, and a subsequent executable
command cannot be issued until t
MRD
is met.
TRUTH TABLE 1: COMMANDS AND DQM OPERATION
1
FUNCTION
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
CS\ RAS\ CAS\ WE\
H
X
L
H
L
L
L
H
DQM
X
X
X
L/H
8
L/H
8
X
X
ADDR
X
X
Bank/Row
Bank/Col
DQs
X
X
X
X
NOTES
X
H
H
L
X
H
H
H
3
4
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
NOTE:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A11 define the op-code written to the mode register, and A12 should be driven LOW.
3. A0-A12 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge
feature; BA0, BA1 determine which bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
L
L
L
H
H
L
L
H
H
L
L
L
Bank/Col
X
Code
Valid
Active
X
4
5
L
L
L
H
X
X
X
6, 7
L
-
-
L
-
-
L
-
-
L
-
-
X
L
H
Op-Code
-
-
X
2
8
8
Active
High-Z
ACTIVE
The ACTIVE command is used to open (or activate) a row
in a particular bank for a subsequent access. The value on the
BA0, BA1 inputs selects the bank, and the address provided
on inputs A0-A12 selects the row. The row remains active (or
open) for accesses until a PRECHARGE command is issued to
that bank. A PRECHARGE command must be issued before
opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access
to an active row. The value on the BA0, BA1 inputs selects the
bank, and the address provided on inputs A0-A8 selects the
starting column location. The value on input A10 determines
whether or not auto precharge is used. If auto precharge is
selected, the row being accessed will be precharged at the end
of the READ burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Read data appears
on the DQs subject to the logic level on the DQM inputs two
clocks earlier. If a given DQM signal was registered HIGH, the
corresponding DQs will be High-Z two clocks later; if the DQM
signal was registered LOW, the DQs will provide valid data.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
相關(guān)PDF資料
PDF描述
AS4SD4M16A2-8 x16 SDRAM
AS5010 Voltage Reference
AS5010GN Voltage Reference
AS5010HN Voltage Reference
AS5010JT Voltage Reference
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS4SD4M16A2-8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM
AS4SD4M16DG-10/IT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4 Meg x 16 SDRAM Synchronous DRAM Memory
AS4SD4M16DG-10/XT 制造商:Micross Components 功能描述:SDRAM-SDR,64MB - Trays
AS4SD4M16DG-8/ET 制造商:Micross Components 功能描述:SDRAM-SDR,64MB - Trays
AS4SD4M16DG-8/IT 制造商:Micross Components 功能描述:SDRAM-SDR,64MB - Trays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*