- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362443 > AS4SD16M16 256000Kbits 16M x 16 Replacement with DSCC 5962-n/a | SDRAM PDF資料下載
參數(shù)資料
| 型號： | AS4SD16M16 |
| 英文描述： | 256000Kbits 16M x 16 Replacement with DSCC 5962-n/a | SDRAM |
| 中文描述： | 256000Kbits 16米x 16置換籍局5962氮/ 1 |內(nèi)存 |
| 文件頁數(shù)： | 3/51頁 |
| 文件大小： | 1071K |
| 代理商： | AS4SD16M16 |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁
S DR A M
AS4SD16M16
Austin Semiconductor, Inc.
AS4SD16M16
Rev. 1.5 6/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
PIN NUMBER
SYMBOL
TYPE
DESCRIPTION
38
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CLK. CLK also
increments the internal burst counter and controls the output
registers.
37
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the
CLK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SLEF REFRESH operation (all banks idle),
ACTIVE POWER-DOWN (row active in any bank) or CLOCK
SUSPEND operation (burst/access in progress). CKE is
synchronous except after the device enters power-down and self
refresh modes, where CKE becomes asynchronous until after
exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
19
CS\
Input
Chip Select: CS\ enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when CS\ is registered HIGH. CS\ provides for external
bank selection on systems with multiple banks. CS\ in considered
part of the command code.
Command Inputs: WE\, CAS\ and RAS\ (along with CS\) define
the command being entered.
Input/Output Mask: DQM is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DWM is sampled HIGH during a WRITE
cycle. The outptu buffers are placed in a High-Z state (two-clock
latency) when DQM is sampled HIGH during a READ cycle.
DQML corresponds to DQ0-DQ7 and DQMH corresponds to
DQ8-DQ15. DQML and DQMH are considered same state when
referenced as DQM.
Bank Address Inputs: BA0 and BA1 define to which bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: A0-A12 are sampled during the ACTIVE
command (row address A0-A12) and READ/WRITE command
(column-address A0-A8; with A10 defining auto precharge) to
select one location out of the memory array in the respective
bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be prechaged (A10 [HIGH]) or bank
selected by (A10 [LOW]). The address inputs also provide the
op-code during LOAD MODE REGISTER COMMAND.
16, 17, 18
WE\, CAS\,
RAS\
Input
15, 39
DQML, DQMU
Input
20, 21
BA0, BA1
Input
23-26, 29-34, 22, 35, 36
A0 - A12
Input
2, 4, 5, 7, 8, 10, 11, 13, 42,
44, 45, 47, 48, 50, 51, 53
40
DQ0 - DQ15
I/O
Data Input/Output: Data bus
NC
---
No Connect: This pin should be left unconnected.
Supplyimmunity.
Supplyimmunity.
Supply Power Supply: +3.3V ±0.3V
3, 9, 43, 49
V
DD
Q
6, 12, 46, 52
V
SS
Q
1, 14, 27
V
DD
28, 41, 54
V
SS
Supply Ground
PIN DESCRIPTIONS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS4SD1M16S-10 | x16 SDRAM |
| AS4SD1M16S-12 | x16 SDRAM |
| AS4SD1M16S-8A | x16 SDRAM |
| AS4SD4M16A2-10 | x16 SDRAM |
| AS4SD4M16A2-8 | x16 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4SD16M16_09 | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:256 MB: 16 Meg x 16 SDRAM Synchronous DRAM Memory |
| AS4SD16M16DG-75 | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:256 MB: 16 Meg x 16 SDRAM Synchronous DRAM Memory |
| AS4SD16M16DG-75/ET | 制造商:Micross Components 功能描述:SDRAM-SDR,256MB - Trays |
| AS4SD16M16DG-75/IT | 制造商:Micross Components 功能描述:SDRAM-SDR,256MB - Trays |
| AS4SD16M16DG-75/IT+ | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:256 MB: 16 Meg x 16 SDRAM Synchronous DRAM Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。