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參數(shù)資料
| 型號： | AS4SD16M16 |
| 英文描述： | 256000Kbits 16M x 16 Replacement with DSCC 5962-n/a | SDRAM |
| 中文描述： | 256000Kbits 16米x 16置換籍局5962氮/ 1 |內(nèi)存 |
| 文件頁數(shù)： | 26/51頁 |
| 文件大?。?/td> | 1071K |
| 代理商： | AS4SD16M16 |
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S DR A M
AS4SD16M16
Austin Semiconductor, Inc.
AS4SD16M16
Rev. 1.5 6/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
26
NOTES (continued):
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank
m
listed in the Command column include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: bank
n
will initiate the auto precharge command when its burst has been interrupted by
bank
m
’s burst.
9. Burst in bank
n
continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank
m
will interrupt
the READ on bank
n
, CAS latency later (Figure 7).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank
m
will
interrupt the READ on bank
n
when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE command
to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank
m
will
interrupt the WRITE on bank
n
when registered (Figure 17), with the data-out appearing CAS latency later. The last valid WRITE
to bank
n
will be data-in registered one clock prior to the READ on bank
m
.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank
m
will
interrupt the WRITE on bank
n
when registered (Figure 15). The last valid WRITE to bank
n
will be data-in registered one clock
prior to the READ to bank
m
.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank
m
will interrupt
the READ on bank
n
, CAS latency later. The PRECHARGE to bank
n
will begin when the READ to bank
m
is registered (Figure
25).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank
m
will interrupt
the READ on bank
n
when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention.
The PRECHARGE to bank
n
will begin when the WRITE to bank
m
is registered (Figure 25).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank
m
will interrupt
the WRITE on bank
n
when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank
n
will begin after
t
WR
is met, where t
WR
begins when the READ to bank
m
is registered. The last valid WRITE to bank
n
will be data-in registered
one clock prior to the READ to bank
m
(Figure 26).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank
m
will interrupt
the WRITE on bank
n
when registered. The PRECHARGE to bank
n
will begin after t
WR
is met, where t
WR
begins when the WRITE
to bank
m
is registered. The last valid WRITE to bank
n
will be data registered one clock prior to the WRITE to bank
m
(Figure 27).
相關PDF資料 |
PDF描述 |
|---|---|
| AS4SD1M16S-10 | x16 SDRAM |
| AS4SD1M16S-12 | x16 SDRAM |
| AS4SD1M16S-8A | x16 SDRAM |
| AS4SD4M16A2-10 | x16 SDRAM |
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相關代理商/技術參數(shù) |
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|---|---|
| AS4SD16M16_09 | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:256 MB: 16 Meg x 16 SDRAM Synchronous DRAM Memory |
| AS4SD16M16DG-75 | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:256 MB: 16 Meg x 16 SDRAM Synchronous DRAM Memory |
| AS4SD16M16DG-75/ET | 制造商:Micross Components 功能描述:SDRAM-SDR,256MB - Trays |
| AS4SD16M16DG-75/IT | 制造商:Micross Components 功能描述:SDRAM-SDR,256MB - Trays |
| AS4SD16M16DG-75/IT+ | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:256 MB: 16 Meg x 16 SDRAM Synchronous DRAM Memory |
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