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參數(shù)資料
| 型號： | AS4LC1M16S1 |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 3.3V 1M × 16 CMOS Synchronous DRAM(3.3V 1M × 16 CMOS同步動態(tài)RAM) |
| 中文描述： | 3.3V的100萬× 16個CMOS同步DRAM（3.3V的100萬× 16個CMOS同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 230K |
| 代理商： | AS4LC1M16S1 |
AS7C3364PFS32A
AS7C3364PFS36A
2/1/01
Alliance Semiconductor
P. 6 of 11
Timing characteristics over operating range
*See “Notes” on page 10.
Key to switching waveforms
Parameter
Symbo
l
–166
–150
–133
–100
Unit
Notes
*
Min
Max
Min
Max
Min
Max
Min
Max
Clock frequency
f
Max
t
CYC
t
CYCF
t
CD
–
166
–
150
–
133
–
100
MHz
Cycle time (pipelined mode)
6
–
6.7
–
7.5
–
10
–
ns
Cycle time (flow-through mode)
10
–
10
–
12
–
12
–
ns
Clock access time (pipelined mode)
–
3.5
–
3.8
–
4.0
–
5.0
ns
Clock access time (flow-through
mode)
t
CDF
–
9
–
10
–
10
–
12
ns
Output enable LOW to data valid
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
OHOE
t
CH
t
CL
t
AS
t
DS
t
WS
t
CSS
t
AH
t
DH
t
WH
t
CSH
t
ADVS
t
ADSPS
t
ADSCS
t
ADVH
t
ADSPH
t
ADSCH
–
3.5
–
3.8
–
4.0
–
5.0
ns
Clock HIGH to output Low Z
0
–
0
–
0
–
0
–
ns
2,3,4
Data output invalid from clock HIGH
1.5
–
1.5
–
1.5
–
1.5
–
ns
2
Output enable LOW to output Low Z
0
–
0
–
0
–
0
–
ns
2,3,4
Output enable HIGH to output High Z
–
3.5
–
3.8
–
4.0
–
4.5
ns
2,3,4
Clock HIGH to output High Z
–
3.5
–
3.8
–
4.0
–
5.0
ns
2,3,4
Output enable HIGH to invalid output
0
–
0
–
0
–
0
–
ns
Clock HIGH pulse width
2.4
–
2.5
–
2.5
–
3.5
–
ns
5
Clock LOW pulse width
2.4
–
2.5
–
2.5
–
3.5
–
ns
5
Address setup to clock HIGH
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
Data setup to clock HIGH
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
Write setup to clock HIGH
1.5
–
1.5
–
1.5
–
2.0
–
ns
6,7
Chip select setup to clock HIGH
1.5
–
1.5
–
1.5
–
2.0
–
ns
6,8
Address hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Data hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Write hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6,7
Chip select hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6,8
ADV setup to clock HIGH
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
ADSP setup to clock HIGH
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
ADSC setup to clock HIGH
1.5
–
1.5
–
1.5
–
2.0
–
ns
6
ADV hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
ADSP hold fromclock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
ADSC hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Undefined/don’t care
Falling input
Rising input
相關PDF資料 |
PDF描述 |
|---|---|
| AS4LC256K16EO | 3.3V 256K×16 CMOS DRAM (EDO)(3.3V 256K×16 CMOS動態(tài)RAM（擴展數(shù)據(jù)總線）) |
| AS4LC4M16S0 | 3.3V 4M × 16 CMOS Synchronous DRAM(3.3V 4M × 16 CMOS同步動態(tài)RAM) |
| AS4LC4M16S0-75TC | 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
| AS4LC4M16S0-8TC | 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AS4LC1M16S1-10TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 2M × 8/1M × 16 CMOS synchronous DRAM |
| AS4LC1M16S1-12TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 2M x 8/1M x 16 CMOS synchronous DRAM |
| AS4LC1M16S1-7TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 2M × 8/1M × 16 CMOS synchronous DRAM |
| AS4LC1M16S1-8TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 2M × 8/1M × 16 CMOS synchronous DRAM |
| AS4LC256K16E0-35JC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K X 16 CMOS DRAM (EDO) |
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