- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381310 > AS4LC1M16S1 (Alliance Semiconductor Corporation) 3.3V 1M × 16 CMOS Synchronous DRAM(3.3V 1M × 16 CMOS同步動(dòng)態(tài)RAM) PDF資料下載
參數(shù)資料
| 型號(hào)： | AS4LC1M16S1 |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 3.3V 1M × 16 CMOS Synchronous DRAM(3.3V 1M × 16 CMOS同步動(dòng)態(tài)RAM) |
| 中文描述： | 3.3V的100萬(wàn)× 16個(gè)CMOS同步DRAM（3.3V的100萬(wàn)× 16個(gè)CMOS同步動(dòng)態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 10/11頁(yè) |
| 文件大?。?/td> | 230K |
| 代理商： | AS4LC1M16S1 |
AS7C3364PFS32A
AS7C3364PFS36A
2/1/01
Alliance Semiconductor
P. 10 of 11
AC test conditions
Output load: see Figure B, except for t
LZC
, t
LZOE
, t
HZOE
, t
HZC
, see Figure C.
Notes
1
2
3
4
5
6
For test conditions, see
AC Test Conditions
, Figures A, B, C.
This parameter measured with output load condition in Figure C.
This parameter is sampled, but not 100% tested.
t
HZOE
is less than t
LZOE
; and t
HZC
is less than t
LZC
at any given temperature and voltage.
tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
Write refers to
GWE
,
BWE
,
BW[a:d].
Chip select refers to
CE0
,
CE1
,
CE2
.
7
8
351
5 pF*
317
D
OUT
GND
Figure C: Output load(B)
*including scope
and jig capacitance
Z
0
= 50
D
OUT
50
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
Input pulse level: GND to 3V See Figure A.
Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
Input and output timing reference levels: 1.5V
V
L
= 1.5V
for 3.3V I/O;
= V
DDQ
/2
for 2.5V I/O
Thevenin equivalent:
+3.3V for 3.3V I/O;
+2.5V for 2.5V I/O
Package Dimensions
100-pin quad flat pack (TQFP)
Dimensions in millimeters
TQFP
Min
0.05
1.35
0.22
0.09
13.90
19.90
0.65 nominal
15.90
21.90
0.45
1.00 nominal
0°
Max
0.15
1.45
0.38
0.20
14.10
20.10
A1
A2
b
c
D
E
e
Hd
He
L
L1
α
16.10
22.10
0.75
7°
He
E
Hd
D
b
e
A1 A2
L1
L
c
α
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS4LC256K16EO | 3.3V 256K×16 CMOS DRAM (EDO)(3.3V 256K×16 CMOS動(dòng)態(tài)RAM（擴(kuò)展數(shù)據(jù)總線）) |
| AS4LC4M16S0 | 3.3V 4M × 16 CMOS Synchronous DRAM(3.3V 4M × 16 CMOS同步動(dòng)態(tài)RAM) |
| AS4LC4M16S0-75TC | 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
| AS4LC4M16S0-8TC | 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
| AS4LC8M8S0 | 3.3V 8M × 8 CMOS Synchronous DRAM(3.3V 8M × 8 CMOS同步動(dòng)態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4LC1M16S1-10TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 2M × 8/1M × 16 CMOS synchronous DRAM |
| AS4LC1M16S1-12TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 2M x 8/1M x 16 CMOS synchronous DRAM |
| AS4LC1M16S1-7TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 2M × 8/1M × 16 CMOS synchronous DRAM |
| AS4LC1M16S1-8TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 2M × 8/1M × 16 CMOS synchronous DRAM |
| AS4LC256K16E0-35JC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K X 16 CMOS DRAM (EDO) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。