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| 型號(hào)： | AS4C4M4E1Q |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 4M × 4 CMOS QuadCAS DRAM(EDO) Family(4M × 4 CMOS QuadCAS動(dòng)態(tài)RAM（擴(kuò)展數(shù)據(jù)總線）) |
| 中文描述： | 4米× 4的CMOS QuadCAS的DRAM（江戶）家庭（4米× 4的CMOS QuadCAS動(dòng)態(tài)隨機(jī)存儲(chǔ)器（擴(kuò)展數(shù)據(jù)總線）） |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 384K |
| 代理商： | AS4C4M4E1Q |
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1
I
CC1
, I
CC3
, I
CC4
, and I
CC6
are dependent on frequency.
2
I
CC1
and I
CC4
depend on output loading. Specified values are obtained with the output open.
3
An initial pause of 200 μs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
4
(max)
≤
V
CC
.
5
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between V
IH
and V
IL
.
6
Operation within the t
RCD
(max) limit insures that t
RAC
(max) can be met. t
RCD
(max) is specified as a reference point ony. If t
RCD
is greater than the
specified t
RCD
(max) limit, then access time is controlled exclusively by t
CAC
.
7
Operation within the t
RAD
(max) limit insures that t
RAC
(max) can be met. t
RAD
(max) is specified as a reference point ony. If t
RAD
is greater than the
specified t
RAD
(max) limit, then access time is controlled exclusively by t
AA
.
8
Assumes three state test load (5 pF and a 380
Thevenin equivalent).
9
Either t
RCH
or t
RRH
must be satisfied for a read cycle.
10 t
OFF
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t
OFF
is referenced fro
rising edge of RAS or CAS, whichever occurs last.
11 t
WCS
, t
WCH
, t
RWD
, t
CWD
and t
AWD
are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.
If t
WS
≥
t
WS
(min) and t
WH
≥
t
WH
(min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the
cycle. If t
RWD
≥
t
RWD
(min), t
CWD
≥
t
CWD
(min) and t
AWD
≥
t
AWD
(min), the cycle is a read-write cycle and the data out will contain data read from the
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of t
CAA
or t
CAC
or t
CPA
14 t
ASC
≥
t
CP
to achieve t
PC
(min) and t
CPA
(max) values.
15 These parameters are sampled and not 100% tested.
16 These characteristics apply to AS4C4M4EOQ 5V devices.
17 These characteristics apply to AS4C4M4E1Q 5V devices.
AC Characteristics assume t
T
= 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, V
IL
(min)
≥
GND and V
IH
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- Access times are measured with output reference levels of V
OH
=
2.4V and V
OL
= 0.4V,
V
IH
= 2.4V and V
IL
= 0.8V
- Input rise and fall times: 2 ns
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Rising input
100 pF*
R2 = 295
R1 = 828
D
out
GND
+5V
Figure A: Equivalent output load
(AS4C4M4E0/AS4C4M4E1)
*including scope
and jig capacitance
*including scope
and jig capacitance
50 pF*
R2 = 295
R1 = 828
D
out
GND
+3.3V
Figure B: Equivalent output load
(AS4C4M4E0/AS4C4M4E1)
Undefined output/don’t care
Falling input
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| AS4C4M4EOQ | 4M × 4 CMOS QuadCAS DRAM(EDO) Family(4M × 4 CMOS QuadCAS動(dòng)態(tài)RAM（擴(kuò)展數(shù)據(jù)總線）) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4C4M4EOQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4M x 4 CMOS QuadCAS DRAM (EDO) family |
| AS4C4M4F0 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5V 4M x 4 CMOS DRAM (Fast Page mode) |
| AS4C4M4F0-50 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 4M×4 CMOS DRAM (Fast Page mode) |
| AS4C4M4F0-50JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM |
| AS4C4M4F0-50JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM |
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