參數(shù)資料
型號(hào): AS29F040-150TI
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類(lèi): PROM
英文描述: 512K X 8 FLASH 5V PROM, 150 ns, PDSO32
封裝: 8 X 20 MM, TSOP-32
文件頁(yè)數(shù): 1/18頁(yè)
文件大?。?/td> 341K
代理商: AS29F040-150TI
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Copyright 2000 Alliance Semiconductor. All rights reserved.
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Organization:512K words × 8 bits
Industrial and commercial temperature
Sector architecture
- Eight 64K byte sectors
- Erase any combination of sectors or full chip
Single 5.0±0.5V power supply for read/write operations
Sector protection
High speed 55/70/90/120/150 ns address access time
Automated on-chip programming algorithm
- Automatically programs/verifies data at specified
address
Automated on-chip erase algorithm
- Automatically preprograms/erases chip or specified
sectors
10,000 write/erase cycle endurance
Low power consumption
- 30 mA maximum read current
- 60 mA maximum program current
- 400 A typical standby current
JEDEC standard software, packages and pinouts
- 32-pin TSOP
- 32-pin PLCC
Detection of program/erase cycle completion
-DQ7 DATA polling
- DQ6 toggle bit
Erase suspend/resume
- Supports reading data from or programming data to
a sector not being erased
Low VCC write lock-out below 2.8V
/RJLF#EORFN#GLDJUDP
X decoder
VCC
VSS
Cell matr
Y decoder
Y gating
Data latch
Chip enable
Ad
d
ress
l
atc
h
Input/output
buffers
Sector protect
Command
register
Program/erase
control
VCC detector
Erase voltage
generator
Program voltage
generator
Timer
A0–A18
CE
OE
STB
Output enable
Logic
WE
DQ0–DQ7
switches
3LQ#DUUDQJHPHQW
VCC
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
DQ4
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
30
29
28
27
26
25
24
23
22
21
20
19
15
16
18
17
32-pin TSOP
32-pin PLCC
1
232
31
30
43
29
28
27
26
25
24
23
21
A7
A6
A5
A4
A3
A2
A1
DQ0
VSS
DQ4
DQ6
DQ1
22
5
6
7
8
9
10
11
13
12
17
16
18
19
20
14
15
DQ2
DQ3
DQ5
A0
A14
A13
A8
A9
A11
OE
A10
DQ7
CE
A16
VCC
A17
A12
A15
A18
WE
AS29F040
6HOHFWLRQ#JXLGH
AS29F040-55
AS29F040-70
AS29F040-90
AS29F040-120 AS29F040-150 Unit
Maximum access time
tAA 55
70
90
120
150
ns
Maximum chip enable access time
tCE 55
70
90
120
150
ns
Maximum output enable access time
tOE 25
30
35
50
55
ns
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