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參數(shù)資料
| 型號(hào)： | AR629A-U9MIO |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | MICROCIRCIT DATA SHEET |
| 中文描述： | MICROCIRCIT數(shù)據(jù)資料 |
| 文件頁(yè)數(shù)： | 9/17頁(yè) |
| 文件大?。?/td> | 63K |
| 代理商： | AR629A-U9MIO |
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MNAR629A-X REV 0A0
MICROCIRCUIT DATA SHEET
Electrical Characteristics
AC: INTER. REG./REC. VALID & INTERRUPT VECTOR STROBE TIMING
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC:
Vdd = Vcc = 5V +5%, Vss = GND, -55 C <TA<+125 C, CL = 50pF
SYMBOL
PARAMETER
CONDITIONS
NOTES
PIN-
NAME
MIN
MAX
UNIT
SUB-
GROUPS
TDAOA
Delay from AE Low
to AO active
Vdd = 4.75V, Vdd = 5.25V
4
0
25
nS
9, 10,
11
TDAOZ
Delay from AE
High to AO
Tri-State
Vdd = 4.75V, Vdd = 5.25V
4
0
40
nS
9, 10,
11
TLRERF
RERF Pulse Width
Vdd = 5V +5%
7T
nS
9, 10,
11
TLXERF
XERF Pulse Width
Vdd = 5V +5%
7T
nS
9, 10,
11
AC: INTERNAL REGISTER/RECEIVE DATA CHARACTERISTICS
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC:
Vdd = Vcc = 5V +5%, Vss = GND, -55 C <TA<+125 C, CL = 50pF
TDBRIVS
Delay from BUSQ
to leading RIVS
Low
Vdd = 5V +5%
5
90T
nS
9, 10,
11
TDBUSQ
Delay from end of
last bit time to
BUSQ
6T-40
7T+46
nS
9, 10,
11
TDBUSQ1
Delay from last
word of string to
BUSQ
5T-40
7T+46
nS
9, 10,
11
TDERR
Delay from BUSQ,
to Error Reg.
valid (non-NRBA)
Vdd = 4.75V, Vdd 5V +5%
7T
64T
nS
9, 10,
11
TDERR
Delay from BUSQ,
to Error Reg.
valid (NRBA)
TG = 2; Vdd = 5V +5%
160T
nS
9, 10,
11
TDERR
Delay from BUSQ,
to Error Reg.
valid(NRBA error
on next to last
date word)
Vdd = 5V +5%
292T
nS
9, 10,
11
TDFSTAC
Delay from RIVS
Low to STAC Low
Vdd = 4.75V, Vdd = 5.25V
5T-30
5T+35
nS
9, 10,
11
TDINT
Delay from BUSQ
to IVR valid
68T
75T
nS
9, 10,
11
TDLRIVS
Time from RIVS
Low to 12th bit
time
5T
nS
9, 10,
11
TDLTRIVS
Delay from
leading RIVS to
trailing RIVS
Vdd = 5V +5%
6
31T
nS
9, 10,
11
9
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