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參數(shù)資料
| 型號(hào)： | AR629A-U9MIO |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | MICROCIRCIT DATA SHEET |
| 中文描述： | MICROCIRCIT數(shù)據(jù)資料 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 63K |
| 代理商： | AR629A-U9MIO |
MNAR629A-X REV 0A0
MICROCIRCUIT DATA SHEET
Electrical Characteristics
AC: INTERNAL REGISTER/RECEIVE DATA CHARACTERISTICS(Continued)
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC:
Vdd = Vcc = 5V +5%, Vss = GND, -55 C <TA<+125 C, CL = 50pF
SYMBOL
PARAMETER
CONDITIONS
NOTES
PIN-
NAME
MIN
MAX
UNIT
SUB-
GROUPS
TDLWM
Delay from BUSQ,
to LWM valid
Vdd = 5V +5%
12T
20T
nS
9, 10,
11
TDRSTAC
Delay from RIVS
High to Stac High
Vdd = 4.75V, Vdd = 5.25V
2T-30
2T+35
nS
9, 10,
11
TDTRIVS
Delay from end of
DMA to trailing
RIVS Low
2T
46T
nS
9, 10,
11
THRAL
AO hold after
leading RIVS
falling edge
Vdd = 5V +5%
65T
nS
9, 10,
11
THRAT
AO hold after
trailing RIVS
falling edge
Vdd = 4.75V, Vdd = 5.25V
4T-35
nS
9, 10,
11
TSAR
AO setup prior to
RIVS falling edge
Vdd = 4.75V, Vdd = 5.25V
2T-35
nS
9, 10,
11
TSDMA
Delay from end of
last bit time to
DMA start
Vdd = 4.75V, Vdd = 5V +5%
13T
20T
nS
9, 10,
11
TWBUSQ
Width of BUSQ
High during data
sync
38T
nS
9, 10,
11
TWBUSQ1
Width Bus Quiet
high during
interstring gap
64T
nS
9, 10,
11
TWRIVS
RIVS pulse Low
width
Vdd = 4.75V, Vdd = 5.25V
2T-10
2T+35
nS
9, 10,
11
TDAOBUSR
Time from AO
valid to DMA
start
Vdd = 5V +5%
30T
nS
9, 10,
11
AC: INTERNAL REGISTER/TRANSMIT DATA CHARACTERISTICS
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC:
Vdd = Vcc = 5V +5%, Vss = GND, -55 C <TA<+125 C, CL = 50pF
TAODMA
Time from AO
valid to DMA
window start
Vdd = 5V +5%
1T
nS
9, 10,
11
TDBUSQ
Delay from end of
last bit time to
BUSQ
6T-40
7T+46
nS
9, 10,
11
TDBUSQ1
Delay from last
word of string to
BUSQ
Vdd = 5V +5%
5T-40
7T+46
nS
9, 10,
11
10
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