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參數(shù)資料
| 型號(hào)： | AP87C54-20 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 16 KBYTES USER PROGRAMMABLE EPROM |
| 中文描述： | 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁(yè)數(shù)： | 14/20頁(yè) |
| 文件大?。?/td> | 290K |
| 代理商： | AP87C54-20 |
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AUTOMOTIVE 87C54/87C54-20
AC TESTING INPUT, OUTPUT WAVEFORMS
270849–17
AC Inputs during testing are driven at V
CC
b
0.5V for a Logic ‘‘1’’
and 0.45V for a Logic ‘‘0’’. Timing measurements are made at V
IH
min for a Logic ‘‘1’’ and V
IL
max for a Logic ‘‘0’’.
FLOAT WAVEFORMS
270849–18
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded V
OH
/V
OL
level occurs.
I
OL
/I
OH
t g
20 mA.
EPROM CHARACTERISTICS
Table 3 shows the logic levels for programming the Program Memory, the Encryption Table and the Lock Bits
and for reading the signature bytes.
Table 3. EPROM Programming Modes
Mode
RST
PSEN
ALE/
PROG
EA/
V
PP
P2.6
P2.7
P3.3
P3.6
P3.7
Program Code Data
H
L
12.75V
L
H
H
H
H
Verify Code Data
H
L
H
H
L
L
L
H
H
Program Encryption
Array Address 0–3FH
H
L
12.75V
L
H
H
L
H
Program Lock
Bits
Bit 1
H
L
12.75V
H
H
H
H
H
Bit 2
H
L
12.75V
H
H
H
L
L
Bit 3
H
L
12.75V
H
L
H
H
L
Read Signature Byte
H
L
H
H
L
L
L
L
L
DEFINITION OF TERMS
ADDRESS LINES:
P1.0–P1.7, P2.0–P2.5 respec-
tively for A0–A13.
DATA LINES:
P0.0–P0.7 for D0–D7.
CONTROL SIGNALS:
RST, PSEN, P2.6, P2.7, P3.3,
P3.6, P3.7
PROGRAM SIGNALS:
ALE/PROG, EA/V
PP
PROGRAMMING THE EPROM
To be programmed, the part must be running with a
4 MHz to 6 MHz oscillator. (The reason the oscillator
needs to be running is that the internal bus is being
used to transfer address and program data to appro-
priate internal EPROM locations.) The address of an
EPROM location to be programmed is applied to
Port 1 and pins P2.0–P2.5 of Port 2, while the code
byte to be programmed into that location is applied
to Port 0. The other Port 2 and 3 pins, RST, PSEN,
and EA/V
PP
should be held at the ‘‘Program’’ levels
indicated in Table 3. ALE/PROG is pulsed low to
program the code byte into the addressed EPROM
location. The setup is shown in Figure 11.
14
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