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參數(shù)資料
| 型號： | AN504 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | Video Crosspoint Switch Simplifies Large Matrix Designs |
| 中文描述： | 視頻交叉點開關(guān)簡化大型矩陣設(shè)計 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 161K |
| 代理商： | AN504 |
AN504
Vishay Siliconix
www.vishay.com FaxBack 408-970-5600
6-8
Document Number: 70610
05-Aug-99
C
(
)
35 W
50 W
35 W
12
10
0
0
10
8
6
4
2
8
6
4
2
Dielectric Constant (Er)
T
50 W
75 W
75 W
ééé
ééé
1/32” Thick Board
W
0.1
1
10
100
120
0
100
80
60
40
20
D
B
C
A
A –1/16” PTFE board
B –1/32” PTFE board
C –1/16” Glass fibre board
D –1/32” Glass fibre board
= 2.74
= 2.74
= 4.5
= 4.5
Track Width (mm)
ééé
ééé
FIGURE 11.
PCB Trace Characteristic Impedance
The inherent channel match of the monolithic DG884 can be
upset by poor external layout. Ideally all input lines to and from
the inputs and outputs should be exactly the same electrical
length to minimize external path (and therefore phase)
differences between the channels.
It may be useful to incorporate transmission lines on the PCB
where the layout forces lengthy track runs. In this case, the
curves in Figure 11 will help define trace geometry to obtain
particular characteristic impedances, such as 50 to 75
.
The importance of good decoupling has already been
mentioned. However, it is worth stressing that component
placement should ensure the absolute minimum track length
from the decoupling point to ground.
Evaluation Results
Figure 12 shows the circuit diagram of the DG884 evaluation
board used with the CLC111 as an input buffer and the CLC410
gain-of-two amplifier at the output. The CLC410s provide
output disable and “l(fā)oss-less” cable termination. Thanks to its
excellent reverse gain characteristics, the input CLC111
provides a solid input impedance of 75 that is independent
of the path setting of the DG884. Ideally, the outputs of the
CLC111s should feed directly to the crosspoint inputs.
However, the capacitive load presented by the DG884 reacts
with the open-loop output impedance of the CLC111 to cause
amplitude peaking by reducing the feedback within the buffer
at increasing frequencies. A series resistance at the output of
the buffer corrects for this. From the CLC111 data sheet, a
value of 12 is required for load capacitances of about 150 pF,
which corresponds to the worst-case on-state capacitance of
the DG884 when set for one input to all outputs.
At the output, the 4.7-k load is chosen as a compromise
between loading and output offset. With this value, offsets will
typically be less than 10 mV.
Figures 13 and 14 show gain and phase plots obtained from
the circuitry shown in Figure 12. Figure 13, the response for
one input to one output, shows a bandwidth of 150 MHz.
Figure 15, the response for one input to four outputs
simultaneously, shows a bandwidth of 55 MHz. Figure 14
shows the measurement setup. The plots are typical of all
channel selections and demonstrate the change in bandwidth
between best- and worst-case path selections. The prototype
showed a maximum delta phase shift of 10 at 30 MHz across
inputs 1 through 8. This equates to a differential delay of 0.9 ns
and is probably due to the input trace layout on the PCB,
adding some 10 cm (worst case) differential path length.
The isolation available from a disabled output (all other outputs
driven and terminated) is in reality a measure of the output
adjacent crosstalk of the prototype and shows a healthy
–50 dB at 30 MHz (Figure 16).
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