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參數資料
| 型號： | AN504 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | Video Crosspoint Switch Simplifies Large Matrix Designs |
| 中文描述： | 視頻交叉點開關簡化大型矩陣設計 |
| 文件頁數： | 6/12頁 |
| 文件大?。?/td> | 161K |
| 代理商： | AN504 |
AN504
Vishay Siliconix
www.vishay.com FaxBack 408-970-5600
6-6
Document Number: 70610
05-Aug-99
(Super-VHS) signals. S-VHS is a much enhanced form of the
VHS system from JVC, and it virtually eliminates signal
degradation caused by multi-separation and combination of
the luminance (Y) and chrominance (C) components that
make up a color video signal. In S-VHS, separate Y and C
signals are fed to the recorder, and at playback, Y and C
signals are obtained for feeding directly to a suitable TV
monitor, i.e., one fitted with an S-connector (SCART).
The S-VHS frequency spectrum extends the peak white
portion of the FM signal from 4.8 MHz to 7 MHz. Thus there is
a need for wideband two input/output crosspoint systems such
as the DG884. Figure 8 outlines the DG884 as a 4 x 2 x 2
crosspoint. A key feature of this use is the reduced change of
capacitance at the inputs, compared to the normal 8 x 4
connection. The worst-case input capacitance for one input to
two outputs is 80 pF, and the worst case for one input to one
output remains the same at 40 pF. Substituting these values
into the HF model outlined above, bandwidth and source
impedance trade-offs can be evaluated.
Power Supplies
The
ground-referenced signal handling (V+, V–, and V
L
= 5 V). The
negative and positive supplies should always be established
first. The logic supply should not be allowed to rise above the
V+ pin during power supply on/off sequencing. This is because
a PN junction exists between the V+ and V
L
pins, and large
currents could flow if this junction becomes forward biased. If
both V+ and V
L
are derived from the same supply there will be
no problems. Figure 9 shows power supplies and decoupling
for bipolar signal operation.
DG884
requires
three
power
supplies
for
The DG884 may be operated in single supply situations (with
V– connected to 0 V) with no loss of logic threshold accuracy.
However, the signal should be offset to +3 V to preserve signal
fidelity through the device.
IN
1
IN
2
IN
3
IN
4
Y
C
Y
C
A
3
A
2
A
1
A
0
B
0
B
1
CS
WR
I/O
I/O Control
Logic
Decode Logic, Switch Drivers
Current Event Latches
Next Event Latches
Switch Matrix
4 Disable Outputs
(Quad Package Only)
RS
SALVO
OUT
1
OUT
2
Y
C
Y
C
Y
C
Y
C
Typical Path Set-Up Might Be:
IN
1
(C, Y Pair)
IN
4
to OUT
2
Pair
or
IN
2
to OUT
1
and OUT
2
to OUT
1
Pair
FIGURE 8.
4
2
2 Crosspoint
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