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參數(shù)資料
| 型號： | AN2897 |
| 英文描述： | Using the eTPU Angle Clock |
| 中文描述： | 使用時鐘角的eTPU |
| 文件頁數(shù)： | 8/32頁 |
| 文件大?。?/td> | 587K |
| 代理商： | AN2897 |
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Using the eTPU Angle Clock, Rev. 0
System Design
Freescale Semiconductor
8
NOTE
Inserting a tooth by asserting IPH will increase the TCR2 count by exactly
one tooth angle by counting forward to the new angle. No counts are
skipped.
If the application determines that the Angle Clock is ahead of the wheel, it can slow the count by asserting
the HOLD bit in the TPR. When this signal is asserted, the Angle Clock hardware immediately suspends
the count until an new tooth is detected. When the new tooth is detected, the Angle Clock operation
resumes from the count it held when the HOLD bit was set.
NOTE
Asserting HOLD stops the TCR2 count for exactly one tooth angle.
There are certain restrictions and limitations to the use of the various signals in the Angle Clock TPR
register.
IPH may be used to reset the counter, if LAST is asserted when IPH is set.
MISSCNT can be used to insert more than three missing teeth with the restriction that if
MISSCNT is to be written on the same tooth as the LAST bit is set, the two fields must be written
together.
Do not use IPH to cancel a HOLD that is in progress. Simply clear the HOLD bit.
When the tick counter is in High Rate mode only IPH and HOLD can have immediate effect. All
other fields in the TPR are buffered until the Angle Clock exits High Rate mode.
If the TICKS field is changed before the Angle Clock goes into Halt mode, the tick counter will
attempt to use the new value immediately after the current tick occurs. Note that the Angle Clock
does not go into Halt mode until approximately one TRR time after the last tick is counted.
Please refer to the Reference Manual for details.
3
System Design
There are four operating conditions that must be considered in the system design process: steady state
operation, acceleration and deceleration, startup, and exception handling. The first two conditions covers
a large majority of the operating time of the system but requires only a small portion of the development
time. Startup is more complex, while exception processing tries to anticipate large numbers of exceedingly
rare error conditions, which must be handled competently without human intervention.
Since the eTPU is only a small slave processor associated with a powerful MCU central processor, the
system approach should be to entrust the steady state operation an much as possible to the eTPU, with
assistance in startup. The eTPU might help in error detection, but since the exception handling may be
complex, the proper systems approach is to use the eTPU to detect anomalies, but correct the errors where
possible in the CPU.
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