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參數(shù)資料
| 型號(hào)： | AN1759 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Add a Non-Volatile Clock to the MC68HC705J1A |
| 中文描述： | 添加非易失時(shí)鐘的MC68HC705J1A |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 316K |
| 代理商： | AN1759 |
Application Note
DS1307 Hardware Interface
AN1759
5
Block Diagram
Figure 2. DS1307 Block Diagram
Serial Interface
TheDS1307supportsthebidirectional,2-wireprotocol.Theprotocolhas
these characteristics:
Any device sending out data is defined as a transmitter.
Any device receiving data is defined as a receiver.
The device controlling the transfer is called the master.
The device being controlled is called the slave.
The master initiates all transactions.
The master always provides the clock for both transmit and
receive operations.
The DS1307 is always considered the slave.
The clock signal is called SCL.
The data signal is called SDA.
All data is sent most significant bit (MSB) first.
Figure 3
shows the 2-wire bus interface between a master and slave.
SQUARE
WAVE OUT
OSCILLATOR
& DIVIDER
SERIAL
BUS INTERFACE
POWER
CONTROL
CONTROL
LOGIC
ADDRESS
REGISTER
REAL-TIME
CLOCK RAM
RAM
56 X 8
X1
X2
V
DD
V
BAT
GND
SQW/OUT
SDA
SCL
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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