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參數(shù)資料
| 型號： | AMC6821SDBQR |
| 英文描述： | Analog Monitor and Control Circuit |
| 中文描述： | 模擬監(jiān)視和控制電路 |
| 文件頁數(shù)： | 27/47頁 |
| 文件大?。?/td> | 547K |
| 代理商： | AMC6821SDBQR |
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P
SMBALERT Pin
SMBALERT Interrupt Behavior
Temperature Back in Limit
(status bit stays set)
High Limit
Temperature
Sticky Status Bit
SMBALERT
Interrupt Disabled
Interrupt Enabled
(
SMBALERT
Rearmed)
Cleared on Read
(temperature below limit)
HANDLING SMBALERT INTERRUPTS
AMC6821
SBAS386A–MAY 2006–REVISED MAY 2006
When a remote temperature sensor failure condition is detected (either short-circuit or open-circuit), the remote
temperature sensor failure bit (RTF) in
Status Register 1
(bit 5, 0x02) is set ('1') and the OVR pin is forced low
when the pin is enabled (RTFIE bit of
Configuration Register 2
is equal to 1). This value indicates a remote
sensor failure condition. Once this condition occurs, the RTF bit remains '1' and the OVR pin stays low until a
power-on reset or software reset is issued, regardless if the failure condition continues thereafter. RTF = 1 also
generates an RTF interrupt through the SMBALERT pin when RTFIE = 1.
The SMBALERT pin is a standard interrupt output defined by SMBus specification revision 2.0. This pin is an
open-drain output pin and is shown in
Figure 23
.
When an out-of-limit event occurs, the proper flag bits in the status registers are set ('1'), and the corresponding
interrupts are generated, if enabled. When an interrupt is generated, the SMBALERT pin asserts low. The host
can poll the device status registers to get the information, or give a response to the SMBALERT interrupt signal.
It is important to note how the SMBALERT output and status bits behave when writing interrupt-handler
software.
Figure 22
shows how the SMBALERT output and status bits behave.
Once a limit is exceeded, the corresponding status bit is set to '1'. The status bit remains set until the error
condition subsides and the status register gets read. The status bits are referred to as being
sticky
because they
remain set until read by software. This design ensures that out-of-limit events cannot be missed if the software is
polling the device periodically. The SMBALERT output remains low for the entire duration that the reading is out
of limits and remains low until the status register has been read. This architecture has implications on how
software handles the interrupt.
Figure 23. How Masking the Interrupt Source Affects SMBALERT
To prevent the system from being tied up while servicing interrupts, it is recommend to handle the SMBALERT
interrupt in this manner:
1. Detect the SMBALERT assertion.
2. Enter the interrupt handler.
3. Read the status registers to identify the interrupt source.
4. Disable the interrupt source by clearing the appropriate enable bit in the configuration registers.
5. Take the appropriate action for a given interrupt source.
6. Exit the interrupt handler.
7. Periodically poll the status registers. If the interrupt source bit has cleared, reset the corresponding interrupt
enable bit to 1. This makes the SMBALERT output and status bits behave as shown in
Figure 23
.
27
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|---|---|
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