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FAN CONTROLLER REGISTERS
AMC6821
SBAS386A–MAY 2006–REVISED MAY 2006
Status Register 2 (Address 0x03, Value After Power-On or Reset = 0x00)
BIT
NAME
R/W
DEFAULT
DESCRIPTION
Status of the THERM pin as an input. When this input is pulled low, THERM-IN = 1, and
the fan is driven at full speed. This bit is cleared when reading this register.
Local temperature over the local THERM limit flag. L-THERM = 1 when the local
temperature is greater than the value of the Local-THERM-Limit register. Otherwise,
L-THERM = 0. When L-THERM = 1, the THERM pin goes low. It also generates a
THERM interrupt through the SMBALERT pin, if enabled (THERMOVIE = 1). This bit is
cleared on a read of
Status Register 1
. Once cleared, this bit is not reasserted until the
temperature falls 5
°
C below the THERM limit, even if the THERM condition persists.
Refer to the
THERM Pin and External Hardware Control
section.
Active control temperature below the PSV (passive cooling) temperature flag. This bit is
set to '1' when the active control temperature is equal to or below the PSV temperature.
Otherwise, this bit is cleared ('0'). LPSV = 1 generates a PSV interrupt on the
SMBALERT pin, if enabled (PSVIE = 1). This bit is cleared when reading this register. If
the active control temperature remains equal to or below the PSV temperature, this bit
reasserts on the next monitoring cycle.
Local temperature over the local critical temperature flag. This bit is set ('1') when the
local temperature is equal to or above the local critical temperature. LTC = 0 if the local
critical temperature is below this value. LTC = 1 asserts the OVR pin low and generates
an LTC interrupt (non-maskable) though the SMBALERT pin. This bit is cleared when
reading this register. If the over-critical limit condition persists, this bit reasserts on the
next monitoring cycle.
Remote temperature over the remote critical temperature flag. This bit is set to '1' when
the remote temperature is equal to or above the remote critical temperature. RTC = 0 if
the remote critical temperature is below this value. RTC = 1 asserts the OVR pin low
and generates an RTC interrupt (non-maskable) though the SMBALERT pin. This bit is
cleared when reading this register. If the over-critical limit condition persists, this bit
reasserts on next monitoring cycle.
Reserved. Reading returns '0'.
Reserved. Reading returns '0'.
Reserved. Reading returns '0'.
7
THERM-IN
R
0
6
L-THERM
R
0
5
LPSV
R
0
4
LTC
R
0
3
RTC
R
0
2
1
0
Reserved
Reserved
Reserved
R
R
R
0
0
0
DCY (Duty Cycle) Register (Address 0x22, Value After Power-On or Reset = 0x55)
BIT
NAME
DCY7 (MSB)
DCY6
DCY5
DCY4
DCY3
DCY2
DCY1
DCY0
DEFAULT
0
1
0
1
0
1
0
1
DESCRIPTION
7 (MSB)
6
5
4
3
2
1
0
DCY CODE
0x00
0x01
... ...
0x40
... ...
0x80
... ...
0xFF
DUTY CYCLE
0%
0.392%
... ...
25%
... ...
50%
... ...
100%
The DCY register stores the value of the PWM duty cycle, 0x00 corresponds to 0%, and 0xFF to 100%. 1LSB
corresponds to 0.392%. Power-on default = 0x55, 33.2%.
In reading operation, the returned data are the actual duty cycle (DCY) value driving the PWM-Out pin. In writing
operation, the data written is the actual DCY driving the PWM-Out pin in the software DCY control mode.
However, in all other control modes, the data being written are not used to drive the PWM. Instead, it is stored in
a temporary register, and controls the PWM immediately after the control mode is changed to the software DCY
control mode.
35
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