參數(shù)資料
型號(hào): AM79C972BKCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
中文描述: 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝: PLASTIC, QFP-160
文件頁(yè)數(shù): 40/130頁(yè)
文件大?。?/td> 1580K
代理商: AM79C972BKCW
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)當(dāng)前第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)
40
Am79C972
Figure 18.
Target Abort
When the preemption occurs after the counter has
counted down to 0, the Am79C972 controller will finish
the current data phase, deassert FRAME, finish the
last data phase, and release the bus. Note that it is im-
portant for the host to program the PCI Latency Timer
according to the bus bandwidth requirement of the
Am79C972 controller. The host can determine this bus
bandwidth requirement by reading the PCI MAX_LAT
and MIN_GNT registers.
Figure 20 assumes that the PCI Latency Timer has
counted down to 0 on clock 7.
Master Abort
The Am79C972 controller will terminate its cycle with a
Master Abort sequence if DEVSEL is not asserted
within 4 clocks after FRAME is asserted. Master Abort
is treated as a fatal error by the Am79C972 controller.
The Am79C972 controller will reset all CSR locations
to their STOP_RESET values. The BCR and PCI con-
figuration registers will not be cleared. Any on-going
network transmission is terminated in an orderly se-
quence. If less than 512 bits have been transmitted
onto the network, the transmission will be terminated
immediately, generating a runt packet. If 512 bits or
more have been transmitted, the message will have the
current FCS inverted and appended at the next byte
boundary to guarantee an FCS error is detected at the
receiving station.
RMABORT (in the PCI Status register, bit 13) will be set
to indicate that the Am79C972 controller has termi-
nated its transaction with a master abort. In addition,
SINT (CSR5, bit 11) will be set to 1. When SINT is set,
INTA is asserted if the enable bit SINTE (CSR5, bit 10)
is set to 1. This mechanism can be used to inform the
driver of the system error. The host can read the PCI
Status register to determine the exact cause of the in-
terrupt. See Figure 21.
Parity Error Response
During every data phase of a DMA read operation,
when the target indicates that the data is valid by as-
serting TRDY, the Am79C972 controller samples the
AD[31:0], C/BE[3:0] and the PAR lines for a data parity
error. When it detects a data parity error, the controller
sets PERR (PCI Status register, bit 15) to 1. When re-
porting of that error is enabled by setting PERREN
(PCI Command register, bit 6) to 1, the Am79C972
controller also drives the PERR signal low and sets
DATAPERR (PCI Status register, bit 8) to 1. The asser-
tion of PERR follows the corrupted data/byte enables
by two clock cycles and PAR by one clock cycle.
Figure 22 shows a transaction that has a parity error in
the data phase. The Am79C972 controller asserts
PERR on clock 8, two clock cycles after data is valid.
The data on clock 5 is not checked for parity, since on
a read access PAR is only required to be valid one
clock after the target has asserted TRDY. The
Am79C972 controller then drives PERR high for one
clock cycle, since PERR is a sustained tri-state signal.
During every data phase of a DMA write operation, the
Am79C972 controller checks the PERR input to see if
the target reports a parity error. When it sees the PERR
input asserted, the controller sets PERR (PCI Status
register, bit 15) to 1. When PERREN (PCI Command
register, bit 6) is set to 1, the Am79C972 controller also
sets DATAPERR (PCI Status register, bit 8) to 1.
FRAME
CLK
AD
IRDY
TRDY
C/BE
DEVSEL
REQ
GNT
PAR
DEVSEL is sampled
2
3
4
5
6
7
ADDR
0000
0111
PAR
PAR
DATA
STOP
1
21485C-21
相關(guān)PDF資料
PDF描述
AM79C972BKIW PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C972BVCW PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C972 PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C972BVIW PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C974 PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C972BKD/W 制造商:Advanced Micro Devices 功能描述:
AM79C972BKD\\W 制造商:Advanced Micro Devices 功能描述:
AM79C972BKD\W 制造商:Advanced Micro Devices 功能描述:
AM79C972BKIW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C972BVC 制造商:Advanced Micro Devices 功能描述: