參數(shù)資料
型號(hào)： AM79C972
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
中文描述： PCnet⑩與OnNow增強(qiáng)10/100 Mbps的快速以太網(wǎng)控制器支持的PCI
文件頁(yè)數(shù)： 127/130頁(yè)
文件大?。?/td> 1580K
代理商： AM79C972
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Am79C972
127
CSR46: Transmit Poll Time Counter
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
TXPOLL
Transmit Poll Time Counter. This
counter is incremented by the
Am79C972 controller microcode
and is used to trigger the transmit
descriptor ring polling operation
of the Am79C972 controller.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR47: Transmit Polling Interval
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 TXPOLLINT
Transmit Polling Interval. This
register contains the time that the
Am79C972 controller will wait be-
tween successive polling opera-
tions. The TXPOLLINT value is
expressed as the two
’
s comple-
ment of the desired interval,
where each bit of TXPOLLINT
represents 1 clock period of time.
TXPOLLINT[3:0] are ignored.
(TXPOLLINT[16] is implied to be
a one, so TXPOLLINT[15] is sig-
nificant and does not represent
the sign of the two
’
s complement
TXPOLLINT value.)
The default value of this register
is 0000h. This corresponds to a
polling interval of 65,536 clock
periods
(1.966
CLK = 33 MHz). The TXPOL-
LINT value of 0000h is created
during the microcode initialization
routine and, therefore, might not
be seen when reading CSR47 af-
ter H_RESET or S_RESET.
ms
when
If the user desires to program a
value for POLLINT other than the
default, then the correct proce-
dure is to first set INIT only in
CSR0. Then, when the initializa-
tion sequence is complete, the
user must set STOP (CSR0, bit
2). Then the user may write to
CSR47 and then set STRT in
CSR0. In this way, the default
value of 0000h in CSR47 will be
overwritten with the desired user
value.
If the user does
not
use the stan-
dard
initialization
(standard implies use of an initial-
ization block in memory and set-
ting the INIT bit of CSR0), but
instead, chooses to write directly
to each of the registers that are
involved in the INIT operation,
then it is imperative that the user
also writes all zeros to CSR47 as
part of the alternative initialization
sequence.
procedure
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR48: Receive Poll Time Counter
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
RXPOLL
Receive Poll Time Counter. This
counter is incremented by the
Am79C972 controller microcode
and is used to trigger the receive
descriptor ring polling operation
of the Am79C972 controller.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR49: Receive Polling Interval
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
RXPOLLINT Receive Polling Interval. This reg-
ister contains the time that the
Am79C972 controller will wait be-
tween successive polling opera-
tions. The RXPOLLINT value is
expressed as the two
’
s comple-
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C972BKC\\W 制造商:Advanced Micro Devices 功能描述:
AM79C972BKC\W 制造商:Advanced Micro Devices 功能描述:
AM79C972BKCW 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C972BKD/W 制造商:Advanced Micro Devices 功能描述:
AM79C972BKD\\W 制造商:Advanced Micro Devices 功能描述:
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