參數資料
型號： AM79C972
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
中文描述： PCnet⑩與OnNow增強10/100 Mbps的快速以太網控制器支持的PCI
文件頁數： 120/130頁
文件大?。?/td> 1580K
代理商： AM79C972
120
Am79C972
write has been performed on this
register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR12: Physical Address Register 0
Note:
Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
PADR[15:0] Physical
Address
Register,
PADR[15:0]. The contents of this
register are loaded from EE-
PROM after H_RESET or by an
EEPROM
read
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the con-
tents of this register are unde-
fined.
command
This register can also be loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR13: Physical Address Register 1
Note:
Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
PADR[31:16]Physical
Address
Register,
PADR[31:16]. The contents of
this register are loaded from EE-
PROM after H_RESET or by an
EEPROM
read
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the con-
tents of this register are unde-
fined.
command
This register can also be loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR14: Physical Address Register 2
Note:
Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
PADR[47:32]Physical
Address
Register,
PADR[47:32].The contents of
this register are loaded from EE-
PROM after H_RESET or by an
EEPROM
read
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the con-
tents of this register are unde-
fined.
command
This register can also be loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR15: Mode
This register
’
s fields are loaded during the Am79C972
controller initialization routine with the corresponding
Initialization Block values, or when a direct register write
has been performed on this register.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15
PROM
Promiscuous
PROM = 1, all incoming receive
frames are accepted.
Mode.
When
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相關代理商/技術參數
參數描述
AM79C972BKC\\W 制造商:Advanced Micro Devices 功能描述:
AM79C972BKC\W 制造商:Advanced Micro Devices 功能描述:
AM79C972BKCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C972BKD/W 制造商:Advanced Micro Devices 功能描述:
AM79C972BKD\\W 制造商:Advanced Micro Devices 功能描述:
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