參數(shù)資料
型號： AM79C961AKCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132
封裝： PLASTIC, QFP-132
文件頁數(shù)： 69/85頁
文件大?。?/td> 1088K
代理商： AM79C961AKCW
Am79C961A
69
P R E L I M I N A R Y
liding signals changes from active to idle. COL stays
active for 2 bit times at the end of a collision.
Signal Quality Error (SQE) Test
(Heartbeat) Function
The SQE function is disabled when the 10BASE-T port
is selected and in Link Fail state.
Jabber Function
The Jabber function inhibits the twisted pair transmit
function of the T-MAU if the TXD
±
circuit is active for an
excessive period (20 ms–150 ms). This prevents any
one node from disrupting the network due to a
‘stuck-on’ or faulty transmitter. If this maximum transmit
time is exceeded, the T-MAU transmitter circuitry is dis-
abled, the JAB bit is set (CSR4, bit 1), and the COL sig-
nal asserted. Once the transmit data stream to the
T-MAU is removed, an “unjab” time of 250 ms – 750 ms
will elapse before the T-MAU deasserts COL and
re-enables the transmit circuitry.
Power Down
The T-MAU circuitry can be made to go into low power
mode. This feature is useful in battery powered or low
duty cycle systems. The T-MAU will go into power down
mode when RESET is active,
coma mode
is active, or
the T-MAU is not selected. Refer to the Power Down
Mode section for a description of the various power
down modes.
Any of the three conditions listed above resets the
internal logic of the T-MAU and places the device into
power down mode. In this mode, the Twisted Pair driver
pins (TXD
±
,TXP
±
) are asserted LOW, and the internal
T-MAU status signals (LNKST, RCVPOL, XMT, RCV
and COLLISION) are inactive.
Once the SLEEP pin is deasserted, the T-MAU will be
forced into the Link Fail state. The T-MAU will move to
the Link Pass state only after 5–6 link beat pulses and/
or a single received message is detected on the RXD
±
pair.
In
Snooze
mode, the T-MAU receive circuitry will
remain enabled even while the SLEEP pin is driven
LOW.
The T-MAU circuitry will always go into power down
mode if RESET is asserted,
coma
is enabled, or the
T-MAU is not selected.
Full Duplex Operation
The PCnet-ISA II supports Full Duplex operation on the
10BASE-T, AUI, and GPSI ports. Full Duplex operation
allows simultaneous transmit and receive activity on
the TXD
±
and RXD
±
pairs of the 10BASE-T port, the
DO
±
and DI
±
pairs of the AUI port, and the TXDAT and
RXDAT pins of the GPSI port. It is enabled by the FDEN
and AUIFD bits located in ISACSR9. When operating in
the Full Duplex mode, the following changes to device
operation are made:
Bus Interface/Buffer Management Unit changes:
1. The first 64 bytes of every transmit frame are not
preserved in the transmit FIFO during transmission
of the first 512 bits transmitted on the network, as
described in the Transmit Exception Conditions sec-
tion. Instead, when Full Duplex mode is active and
a frame is being transmitted, the XMTFW bits
(CSR80, bits 9, 8)
always
govern when transmit
DMA is requested.
2. Successful reception of the first 64 bytes of every
receive frame is not a requirement for Receive DMA
to begin as described in the Receive Exception
Conditions section. Instead, receive DMA will be
requested as soon as either the RCVFW threshold
(CSR80 bits 12, 13) is reached or a complete valid
receive frame is in the Receive FIFO, regardless of
length. This receive FIFO operation is identical to
when the RPA bit (CSR124, bit 3) is set during Half
Duplex mode operation.
MAC Engine changes:
1. Changes to the Transmit Deferral mechanism:
A. Transmission is not deferred while receive is
active.
B. The Inter Packet Gap (IPG) counter which gov-
erns transmit deferral during the IPG between
back-to-back transmits is started when transmit
activity for the first packet ends instead of when
transmit
and
carrier activity ends.
2. When the AUI or GPSI port is active, Loss of Carrier
(LCAR) reporting is disabled (LCAR is still reported
when the 10BASE-T port is active if a packet is
transmitted while in the Link Fail state).
3. The 4.0
μ
s carrier sense blinding period after a
transmission during which the SQE test normally
occurs is disabled.
4. When the AUI or GPSI port is active, the SQE Test
error (Collision Error, CERR) reporting is disabled
(CERR is still reported when the 10BASE-T port is
active if a packet is transmitted while in the Link Fail
state).
5. The collision indication input to the MAC Engine is
ignored.
T-MAU changes:
1. The transmit to receive loopback path in the
T-MAU is disabled.
2. The collision detect circuit is disabled.
3. The “heartbeat” generation (SQE Test function)
is disabled.
相關PDF資料
PDF描述
AM79C961AKC PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961A PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961AKIW PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961AVCW PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961AVIW PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
相關代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C961AKI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C961AKI/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C961AKIW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
AM79C961APDLUTS 制造商:Advanced Micro Devices 功能描述:
AM79C961AVC 制造商:Rochester Electronics LLC 功能描述: 制造商:Advanced Micro Devices 功能描述:LAN Node Controller, 144 Pin, TQFP
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*