參數(shù)資料
型號(hào): AM79C961AKCW
廠商: ADVANCED MICRO DEVICES INC
元件分類(lèi): 微控制器/微處理器
英文描述: PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述: 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132
封裝: PLASTIC, QFP-132
文件頁(yè)數(shù): 50/85頁(yè)
文件大?。?/td> 1088K
代理商: AM79C961AKCW
50
Am79C961A
P R E L I M I N A R Y
The following chart and its bit descriptions show the
internal command registers associated with the Plug
and Play operation. These registers control the
PCnet-ISA II controller Plug and Play operation.
PCnet–ISA II’s Legacy Bit Feature
Description
The current PCnet-ISA II chip is designed such that it
always responds to Plug and Play configuration soft-
ware. There are situations where this response to the
Plug and Play software is undesirable. An example of
this is when a fixed configuration is required, or when
the only possible resource available for the PCnet-ISA
II conflicts with a present but not used resource such as
IRQ, or when the chip is used in a system with a buggy
PnP BIOS.
To function in the situations above, a new feature has
been added to the PCnet-ISA II chip. This new feature
makes the chip ignore the PnP software’s special initi-
ation key sequence (6A). This will effectively turn the
chip into the “Legacy” mode operation, where it will be
visible in the I/O space, and only special setup pro-
grams will be able to reconfigure it. In case the
EEPROM is missing, empty, or corrupted, the chip will
still recognize AMD’s special initiation key sequence
(6B).
To enable this feature, a one has to be written into the
LGCY_EN bit, which is bit 6 of the Plug and Play regis-
ter 0xF0. A preferred method would be set this bit in
the Vendor Byte (PnP 0xF0) field of the EEPROM
located in word offset 0x1A.
Plug and
Play Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x60
0
0
0
0
0
0
1
IOAM3
0x61
IOAM2
IOAM1
IOAM0
0
0
0
0
0
0x70
0
0
0
0
IRQ3
IRQ2
IRQ1
IRQ0
0x71
0
0
0
0
0
0
IRQ_LVL
IRQ_TYPE
0x74
0
0
0
0
0
DMA2
DMA1
DMA0
0x40
0
0
0
0
1
1
0
BPAM3
0x41
BPAM2
BPAM1
BPAM0
0
0
0
0
0
0x42
0
0
0
0
0
0
BP_16B
0
0x43
1
1
1
1
1
1
1
BPSZ3
0x44
BPSZ2
BPSZ1
BPSZ0
0
0
0
0
0
0x48
0
0
0
0
1
1
SRAM4
SRAM3
0x49
SRAM2
SRAM1
SRAM0
0
0
0
0
0
0x4A
0
0
0
0
0
0
SR16B
0
0x4B
1
1
1
1
1
1
1
SRSZ3
0x4c
SRSZ2
SRSZ1
SRSZ0
0
0
0
0
0
0xF0
0
LGCY_EN
DXCVRP
FL_SEL
BP_CS
APROM_EN
AEN_CS
IO_MODE
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