- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C961AKCW (ADVANCED MICRO DEVICES INC) PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA PDF資料下載
參數(shù)資料
| 型號： | AM79C961AKCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 61/85頁 |
| 文件大?。?/td> | 1088K |
| 代理商： | AM79C961AKCW |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁當(dāng)前第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
Am79C961A
61
P R E L I M I N A R Y
Following this poll, and regardless of the outcome of
this poll, transfers of receive data from the FIFO may
begin.
Regardless of ownership of the second receive
descriptor, the PCnet-ISA II controller will continue to
perform receive data DMA transfers to the first buffer,
using burst-cycle DMA transfers. If the packet length
exceeds the length of the first buffer, and the
PCnet-ISA II
controller does not own the second buffer,
ownership of the current descriptor will be passed back
to the system by writing a zero to the OWN bit of RMD1
and status will be written indicating buffer (BUFF = 1)
and possibly overflow (OFLO = 1) errors.
If the packet length exceeds the length of the first (cur-
rent) buffer, and the PCnet-ISA II controller does own
the second (next) buffer, ownership will be passed back
to the system by writing a zero to the OWN bit of RMD1
when the first buffer is full. Receive data transfers to the
second buffer may occur before the PCnet-ISA II con-
troller proceeds to look ahead to the ownership of the
third buffer. Such action will depend upon the state of
the FIFO when the status has been updated on the first
descriptor. In any case, lookahead will be performed to
the third buffer and the information gathered will be
stored in the chip, regardless of the state of the owner-
ship bit. As in the transmit flow, lookahead operations
are performed only once.
This activity continues until the PCnet-ISA II controller
recognizes the completion of the packet (the last byte of
this receive message has been removed from the FIFO).
The PCnet-ISA II controller will subsequently update the
current RDTE status with the end of packet (ENP) indi-
cation set, write the message byte count (MCNT) of the
complete packet into RMD2 and overwrite the “current”
entries in the CSRs with the “next” entries.
Media Access Control
The Media Access Control engine incorporates the
essential protocol requirements for operation of a com-
pliant Ethernet/802.3 node, and provides the interface
between the FIFO sub-system and the Manchester
Encoder/Decoder (MENDEC).
This section describes operation of the MAC engine
when operating in Half Duplex mode. When in Half
Duplex mode, the MAC engine is fully compliant to Sec-
tion 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard 1990
Second Edition) and ANSI/IEEE 802.3 (1985). When
operating in Full Duplex mode, the MAC engine behavior
changes as described in the Full Duplex Operation sec-
tion.
The MAC engine provides programmable enhanced
features designed to minimize host supervision and pre
or post-message processing. These features include
the ability to disable retries after a collision, dynamic
FCS generation on a packet-by-packet basis, and auto-
matic pad field insertion and deletion to enforce
minimum frame size attributes.
The two primary attributes of the MAC engine are:
I
Transmit and receive message data encapsulation
— Framing (frame boundary delimitation, frame
synchronization)
— Addressing (source and destination address
handling)
— Error detection (physical medium transmission
errors)
I
Media access management
— Medium allocation (collision avoidance)
— Contention resolution (collision handling)
Transmit and Receive Message Data Encapsulation
The MAC engine provides minimum frame size
enforcement for transmit and receive packets. When
APAD_XMT = 1 (bit 11 in CSR4), transmit messages
will be padded with sufficient bytes (containing 00h) to
ensure that the receiving station will observe an infor-
mation field (destination address, source address,
length/type, data and FCS) of 64-bytes. When
ASTRP_RCV = 1 (bit 10 in CSR4), the receiver will
automatically strip pad bytes from the received mes-
sage by observing the value in the length field, and
stripping excess bytes if this value is below the mini-
mum data size (46 bytes). Both features can be inde-
pendently over-ridden to allow illegally short (less than
64 bytes of packet data) messages to be transmitted
and/or received. The use of these features reduce bus
bandwidth usage because the pad bytes are not trans-
ferred to or from host memory.
Framing (frame boundary delimitation, frame
synchronization)
The MAC engine will autonomously handle the con-
struction of the transmit frame. Once the Transmit FIFO
has been filled to the predetermined threshold (set by
XMTSP in CSR80), and providing access to the chan-
nel is currently permitted, the MAC engine will com-
mence the 7-byte preamble sequence (10101010b,
where first bit transmitted is a 1). The MAC engine will
subsequently append the Start Frame Delimiter (SFD)
byte (10101011b) followed by the serialized data from
the Transmit FIFO. Once the data has been completed,
the MAC engine will append the FCS (most significant
bit first) which was computed on the entire data portion
of the message.
Note that the user is responsible for the correct order-
ing and content in each of the fields in the frame,
including the destination address, source address,
length/type and packet data.
The receive section of the MAC engine will detect an
incoming preamble sequence and lock to the encoded
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C961AKC | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961A | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961AKIW | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961AVCW | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961AVIW | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961AKI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C961AKI/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C961AKIW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961APDLUTS | 制造商:Advanced Micro Devices 功能描述: |
| AM79C961AVC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Advanced Micro Devices 功能描述:LAN Node Controller, 144 Pin, TQFP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。