- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C961AKCW (ADVANCED MICRO DEVICES INC) PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA PDF資料下載
參數(shù)資料
| 型號： | AM79C961AKCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 54/85頁 |
| 文件大小： | 1088K |
| 代理商： | AM79C961AKCW |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁當(dāng)前第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
54
Am79C961A
P R E L I M I N A R Y
Plug and Play registers. Flash Select is cleared
by RESET (default).
In bus master mode, BPCS becomes Flash_OE and
IRQ12 becomes Flash_WE. The Flash ROM devices
CS pin is connected to ground.
In shared memory mode, BPCS becomes Flash_CS
and IRQ12 becomes the static RAM Chip Select, and
the SROE and SRWE signals are connected to both
the SRAM and Flash devices.
Optional IEEE Address PROM
Normally, the Ethernet physical address will be stored
in the EEPROM with the other configuration data. This
reduces the parts count, board space requirements,
and power consumption. The option to use a standard
parallel 8 bit PROM is provided to manufacturers who
are concerned about the non-volatile nature
of EEPROMs.
To use a 8 bit parallel PROM to store the IEEE address
data instead of storing it in the EEPROM, the
APROM_EN bit is set in the Plug and Play registers by
the EEPROM upon RESET. IRQ15 is redefined by the
setting of this bit to be APCS, or ADDRESS PROM
CHIP SELECT. This pin is connected to an external 8
bit PROM, such as a 27LS19. The address pins of the
PROM are connected to the lower address pins of the
ISA bus, and the data lines are connected to the private
data bus.
In this mode, any accesses to the IEEE address will be
passed to the external PROM and the data will be
passed through the PCnet-ISA II controller to
the system data bus.
EISA Configuration Registers
The PCnet-ISA II controller has support for the 4-byte
EISA Configuration Registers. These are used in EISA
systems to identify the card and load the appropriate
configuration file for that card. This feature is enabled
using bit 10 of ISACSR2. When set to 1, the EISA Con-
figuration registers will be enabled and will be read at
I/O location 0xC80–0xC83. The contents of these 4
registers are stored in the EEPROM and are automat-
ically read in at RESET.
Bus Interface Unit (BIU)
The bus interface unit is a mixture of a 20 MHz state
machine and asynchronous logic. It handles two types
of accesses; accesses where the PCnet-ISA II control-
ler is a slave and accesses where the PCnet-ISA II con-
troller is the Current Master.
In slave mode, signals like IOCS16 are asserted and
deasserted as soon as the appropriate inputs
are received. IOCHRDY is asynchronously driven LOW
if the PCnet-ISA II controller needs a wait state. It is
released synchronously when the PCnet-ISA II control-
ler is ready.
When the PCnet-ISA II controller is the Current Master,
all the signals it generates are synchronous to the
on-chip 20 MHz clock.
DMA Transfers
The BIU will initiate DMA transfers according to the
type of operation being performed. There are three pri-
mary types of DMA transfers:
1. Initialization Block DMA Transfers
During initialization, the PCnet-ISA II transfers 12
words from the initialization block in memory to internal
registers. These 12 words are transferred through dif-
ferent bus mastership period sequences, depending on
whether the TIMER bit (CSR4, bit 13) is set and, if
TIMER is set, on the value in the Bus Activity Timer
register (CSR82).
If the TIMER bit is reset (default), the 12 words are
always transferred during three separate bus master-
ship periods. During each bus mastership period, four
words (8 bytes) will be read from contiguous memory
addresses.
If the TIMER bit is set, the 12 words may be transferred
using anywhere from 1 to 3 bus mastership periods,
depending on the value of the Bus Activity Timer regis-
ter (CSR82). During each bus mastership period, a
minimum of four words (8 bytes) will be read from con-
tiguous memory addresses. If the TIMER bit is set and
the value in the Bus Activity Timer register allows it, 8
or all 12 words of the initialization block are read during
a single bus mastership period.
2. Descriptor DMA Transfers
Descriptor DMA transfers are performed to read or
write to transmit or receive descriptors. All transmit and
receive descriptor READ accesses require 3 word
reads (TMD1, TMD0, then TMD2 for transmit descrip-
tors and RMD1, RMD0, then RMD2 for receive descrip-
tors). Transmit and receive descriptor WRITE accesses
to unchained descriptors or the last descriptor in a
chain (ENP set) require 2 word writes (TMD1 then
TMD3 for transmit and RMD1 then RMD3 for receive).
Transmit and receive descriptor WRITE accesses to
chained descriptors that do not have ENP set require 1
word write (TMD1 for transmit and RMD1 for receive).
During descriptor write accesses, only the bytes which
need to be written are written, as controlled by the SA0
and SBHE pins.
If the TIMER bit is reset (default), all accesses during a
single bus mastership period will be either all read or all
write and will be to only one descriptor. Hence, when
the TIMER bit is reset, the bus mastership periods for
descriptor accesses are always either 3, 2, or 1 cycles
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C961AKC | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961A | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961AKIW | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961AVCW | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961AVIW | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961AKI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C961AKI/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C961AKIW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961APDLUTS | 制造商:Advanced Micro Devices 功能描述: |
| AM79C961AVC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Advanced Micro Devices 功能描述:LAN Node Controller, 144 Pin, TQFP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。