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參數(shù)資料
| 型號： | AM79C961A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | PCnet⑩- 2跳線的ISA，全雙工單芯片以太網(wǎng)控制器為ISA |
| 文件頁數(shù)： | 84/85頁 |
| 文件大?。?/td> | 1088K |
| 代理商： | AM79C961A |
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Am79C961A
P R E L I M I N A R Y
MAGIC PACKET OPERATION
In the Magic Packet mode, PCnet-ISA II completes any
transmit and receive operations in progress, suspends
normal activity, and enters into a state where only a
Magic Packet could be detected. A Magic Packet frame
is a frame that contains a data sequence which repeats
the Physical Address (PADR[47:00]) at least sixteen
times frame sequentially, with bit[00] received first. In
Magic Packet suspend mode, the PCnet-ISA II remains
powered up. Slave accesses to the PCnet-ISA II are
still possible, the same as any other mode. All of the
received packets are flushed from the receive FIFO. An
LED and/or interrupt pin could be activated, indicating
the receive of a Magic Packet frame. This indication
could be used for a variety of management tasks.
Magic Packet Mode Activation
This mode can be enabled by either software or exter-
nal hardware means, but in either case, the MP_MODE
bit (CSR5, bit 1) must be set first.
Hardware Activation.
This is done by driving the
SLEEP pin low. Deasserting the SLEEP pin will return
the PCnet-ISA II to normal operation.
Software Activation.
This is done by setting the
MP_ENBL bit (CSR5, bit 2). Resetting this bit will return
the PCnet-ISA II to normal operation.
Magic Packet Receive Indicators
The reception of a Magic Packet can be indicated either
through one of the LEDs 1, 2 or 3, and/or the activation
of the interrupt pin. MP_INT bit (CSR5, bit 4) will also
be set upon the receive of the Magic Packet.
LED Indication
. Either one of the LEDs 1, 2, or 3 could
be activated by the receive of the Magic Packet. The
“Magic Packet enable” bit (bit 9) in the ISACSR 5, 6 or
7 should be set to enable this feature. Note that the
polarity of the LED2 could be controlled by the
LEDXOR bit (ISACSR6, bit 14). The LED could be
deactivated by setting the STOP bit or resetting the
MP_ENBL bit (CSR5, bit 2).
Interrupt Indication
. Interrupt pin could be activated
by the receive of the Magic Packet. The MP_I_ENBL bit
(CSR5, bit 3) and IENA bit (CSR0, bit 6) should be set
to enable this feature.
Loopback Operation
Loopback is a mode of operation intended for system
diagnostics. In this mode, the transmitter and receiver
are both operating at the same time so that the
controller receives its own transmissions. The control-
ler provides two types of internal loopback and three
types of external loopback. In internal loopback mode,
the transmitted data can be looped back to the receiver
at one of two places inside the controller without actu-
ally transmitting any data to the external network. The
receiver will move the received data to the next receive
buffer, where it can be examined by software. Alterna-
tively, external loopback causes transmissions to go
off-chip. For the AUI port, frame transmission occurs
normally and assumes that an external MAU will loop
the frame back to the chip. For the 10BASE-T port, two
external loopback options are available, both of which
require a valid link pass state and both of which trans-
mit data frames at the RJ45 interface. Selection of
these modes is defined by the TMAU_LOOPE bit in
ISACSR2. One option loops the data frame back inside
the chip, and is compatible with a ‘live’ network. The
other option requires an external device (such as a
‘loopback plug’) to loop the data back to the chip, a
function normally not available on a 10BASE-T
network.
The PCnet-ISA II chip has two dedicated FCS genera-
tors, eliminating the traditional LANCE limitations on
loopback FCS operation. The receive FCS generation
logic is always enabled. The transmit FCS generation
logic can be disabled (to emulate LANCE type loop-
back operation) by setting the DXMTFCS bit in the
Mode register (CSR15). In this configuration, software
must generate the FCS and append the four FCS bytes
to the transmit frame data.
The loopback facilities of the MAC Engine allow full
operation to be verified without disturbance to the net-
work. Loopback operation is also affected by the state
of the Loopback Control bits (LOOP, MENDECL, and
INTL) in CSR15. This affects whether the internal
MENDEC is considered part of the internal or external
loop- backpath.
The receive FCS generation logic in the PCnet-ISA II
chip is used for multicast address detection. Since this
FCS logic is always enabled, there are no restrictions
to the use of multicast addressing while in loopback
mode.
When performing an internal loopback, no frame will be
transmitted to the network. However, when the
PCnet-ISA II controller is configured for internal loop-
back the receiver will not be able to detect network
traffic. External loopback tests will transmit frames onto
the network if the AUI port is selected, and the
PCnet-ISA II controller will receive network traffic while
configured for external loopback when the AUI port is
selected. Runt Packet Accept is automatically enabled
when any loopback mode is invoked.
Loopback mode can be performed with any frame size.
Runt Packet Accept is internally enabled (RPA bit in
CSR124 is not affected) when any loopback mode is
invoked. This is to be backwards compatible to the
LANCE (Am7990) software.
LEDs
The PCnet-ISA II controller’s LED control logic allows
programming of the status signals, which are displayed
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| AM79C961A_00 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
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| AM79C961AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
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